Scan flip-flop providing both scan and propagation delay...

Details Scan flip-flop providing both scan and propagation delay... Scan flip-flop providing both scan and propagation delay...

2000-07-12

2002-12-17

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

With test facilitating feature

C326S095000, C714S726000, C327S203000

Reexamination Certificate

active

06496030

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device which has a design that facilitates testing the manufacturing state of a wafer to check whether the semiconductor integrated circuit device satisfies a desired circuit performance based on a design standard.
BACKGROUND OF THE INVENTION
Usually, from the viewpoint of improving the reliability in the operation of a semiconductor integrated circuit device, it is necessary to check a wafer in a manufacturing state of the semiconductor integrated circuit device to check whether the semiconductor integrated circuit device satisfies a desired circuit performance or not. As methods for performing such a test, there is known a method of adding a group of gate circuits (a long delay path) to the semiconductor integrated circuit device and a method of adding a scan path group, constructed based on what is called a design for testability, to the semiconductor integrated circuit device.
FIG. 4
is a diagram that shows a circuit construction of the above gate circuit group. This gate circuit group is constructed to have logic gates such as AND gates and OR gates connected in series of several hundred stages between an input buffer and an output buffer. Such a gate circuit group is located within a semiconductor integrated circuit device at a position where it operates independent of the operation of the circuits that achieve the primary functions of the semiconductor integrated circuit device. A test using this gate circuit group is carried out such that a desired signal is first input into an input terminal (IN), and propagation delay time of this signal is monitored when it is output from an output terminal (OUT). The circuitry is diagnosed based on this propagation delay time.
This test is based on the fact that logic gates (semiconductors) on the same semiconductor integrated circuit device, or the same wafer, have substantially the same characteristics, and therefore, the circuit diagnosis of the gate circuit group can be equivalently applied to the diagnosis of the logic circuits that achieve the primary functions of the semiconductor integrated circuit device.
On the other hand, circuits that constitute a scan path group are designed so that they are built into the logic circuits that achieve the primary functions within the semiconductor integrated circuit device. The performance of the circuitry is diagnosed by verifying an output result corresponding to a predetermined scan signal that is input into the logic circuits (hereinafter to be referred to as a scan test). A multi-stage connection of scan flip-flop circuits is known as a representative example of the circuitry that forms the scan path group.
Generally, within a semiconductor integrated circuit device that has been designed to be built in with a scan path group, that is, within a scan-designed semiconductor integrated circuit device, there are disposed a plurality of scan flip-flops that input or output normal-operation input signals to be input during a normal operation or circuit-diagnosis input signals to be input for carrying out the test, at an input pre-stage and an output post-stage of sequential circuits or combination circuits (hereinafter to be collectively referred to as combination circuits) that achieve the primary functions of the semiconductor integrated circuit device.
The plurality of scan flip-flops disposed at the input pre-stage (hereinafter to be referred to as a flip-flop pre-stage section) are constructed such that, when the normal operation mode has been selected, a plurality of externally-applied normal signals are input in parallel to the flip-flop pre-stage section of the combination circuits, and so that, when the test mode has been selected, circuit diagnosis input signals are delivered in series to the flip-flop pre-stage section.
Similarly, the plurality of scan flip-flops disposed at the output post-stage (hereinafter to be referred to as a flip-flop post-stage section) are constructed such that, when the normal operation mode has been selected, a plurality of signals output from the combination circuits are input in parallel to the post-stage section, and that, when the test mode has been selected, circuit diagnosis input signals that have been delivered in series at the flip-flop pre-stage section are delivered in series to the flip-flop post-stage section.
Based on the above arrangement, during the normal operation mode, the scan path group can execute the primary input and output operations of the combination circuits. During the test mode, the scan path group can sequentially take out the output of the combination circuits obtained from the input of the circuit diagnosis input signals, from a predetermined scan flip-flop at the flip-flop post-stage section. Thus, it is possible to diagnose the combination circuits based on the result of this output.
FIG. 5
is a diagram that shows a circuit construction of the above-described scan flip-flop. This scan flip-flop consists of a selector
101
, a first latch
102
, a second latch
103
, and an inverter G
10
for inverting a clock signal T. The selector
101
selectively outputs a normal operation input signal D and a circuit diagnosis input signal SI, according to a mode changeover input signal SMC.
The selector
101
consists of an inverter G
111
that inverts the mode changeover input signal SMC, an N-channel transmission gate N
111
that receives the mode changeover input signal SMC from a control terminal (a gate) and receives the normal operation input signal D from one contact terminal (a source or a drain), and an N-channel transmission gate N
112
that receives the output signal of the inverter G
111
at a control terminal (a gate) and receives the circuit diagnosis input signal SI from one contact terminal (a source or a drain). The other contact terminal (a drain or a source) of the N-channel transmission gate N
111
and the other contact terminal (a drain or a source) of the N-channel transmission gate N
112
are connected with each other. The circuit diagnosis input signal SI or the normal operation input signal D is selectively output from the node between these contact terminals.
The first latch
102
receives the normal operation input signal D or the circuit diagnosis input signal SI output by the selector
101
, holds the received signal and transmits it to the second latch
103
at the next stage, according to the clock signal T.
The first latch
102
consists of an N-channel transmission gate N
121
that receives the clock signal T from a contact terminal (a gate) and whose one contact terminal (a source or a drain) is connected to an output terminal of the selector
101
as an input terminal of the first latch
102
. The first latch
102
also has an N-channel transmission gate N
122
that receives the output of the inverter G
10
at a control terminal (a gate) and whose one contact terminal (a source or a drain) is connected to the other contact terminal (a drain or a source) of the N-channel transmission gate N
121
. The first latch
102
also has an inverter G
121
whose input terminal is connected to the other contact terminal (a drain or a source) of the N-channel transmission gate N
121
and whose output terminal is also an output terminal of the first latch
102
. The first latch further has an inverter G
122
whose input terminal is connected to the output terminal of the inverter G
121
and whose output terminal is connected to the other contact terminal (a drain or a source) of the N-channel transmission gate N
122
.
The second latch
103
is a circuit that holds and outputs a signal output from the first latch
102
according to the clock signal T. The second latch
103
consists of an N-channel transmission gate N
131
that receives the output of the inverter G
10
from a control terminal (a gate) and whose one contact terminal (a source or a drain) is connected to an output terminal of the first latch
102
as an input terminal of the second latch
103
. The second latch
103
also has an N-channel transmission

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