Scan flip-flop circuit, logic macro, scan test circuit, and...

Details Scan flip-flop circuit, logic macro, scan test circuit, and... Scan flip-flop circuit, logic macro, scan test circuit, and...

2005-07-19

2005-07-19

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06920594

ABSTRACT:
A scan flip-flop circuit has a scan test data output terminal QT in addition to a Q terminal and a /Q terminal. To the QT terminal, the data that have been held in an internal data holding circuit is transferred via a tristate buffer that has been incorporated in advance. The drive capability of the tristate buffer is determined so that a propagation delay time is obtained and the scan test data outputted from the QT terminal is propagated to the scan test data input terminal DT of the next stage scan flip-flop circuit. Consequently, during scan testing, a sufficient delay is added to the output from the scan flip-flop circuit, and hold errors do not easily occur.

REFERENCES:
patent: 5294837 (1994-03-01), Takase et al.
patent: 6182256 (2001-01-01), Qureshi
patent: 6389566 (2002-05-01), Wagner et al.
patent: 63-263480 (1988-10-01), None

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