Scan flip-flop and methods for controlling the entry of data the

Details Scan flip-flop and methods for controlling the entry of data the Scan flip-flop and methods for controlling the entry of data the

1996-09-24

1999-08-17

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

365201, G01R 3128

Patent

active

059387823

ABSTRACT:
A scan data flip-flop having improved timing characteristics is provided. A scan flip-flop includes: a first data input coupled with a first latch; a second data input coupled with said first latch; a clock input coupled with said first latch; a data control input; and a data controller operably coupled with said clock input and said data control input and said first latch; said data controller being configured to generate an enable signal responsive to a clock signal from said clock input and a data control signal from said data control input, and said enable signal to control the input of data into said first latch. The normal or first data input signal is preferably directly applied to the first latch within the scan data flip-flop according to the present invention. The data controller of the scan data flip-flop according to the present invention is preferably void of a multiplexer. A method for controlling the entry of data into a scan data flip-flop is also provided.

REFERENCES:
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patent: 5596584 (1997-01-01), Warren
patent: 5646567 (1997-07-01), Felix
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Principles of CMOS VLSI Design: A System Perspective by Weste and Eshraghian, pp. 485-492 (1993).
Passport CB60SY240-0.6 Micron, 5 Volt Optimum Silicon Library by Compass Design Automation, pp. 243-244, 270-271 (1996).
Scan Tools--Scan Design User Guide V8R4.2 by Compass Design Automation, pp. 3-2--3-4 (1993).

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