Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-12-14
2010-12-28
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C714S727000, C714S729000
Reexamination Certificate
active
07861128
ABSTRACT:
A scan element with self scan-mode toggle is described. In an example, the scan element is configured to automatically switch between a capture mode and a scan mode. In the capture mode, data is captured from logic under test. In the scan mode, the captured data is scanned out for testing. The scan elements each include a shift register that serves a dual purpose of providing control for determining when the scan element is to switch from the capture mode and the scan mode, as well as providing a location to store captured data.
REFERENCES:
patent: 6813738 (2004-11-01), Whetsel, Jr.
patent: 7640475 (2009-12-01), Ravikumar et al.
patent: 2006/0100810 (2006-05-01), Van De Logt et al.
patent: 2008/0307280 (2008-12-01), Putman et al.
Bapat, Shekhar, “Methods of Testing a User Design in a Programmable Integrated Circuit”, U.S. Appl. No. 11/500,526, filed Aug. 8, 2006, pp. 1-18, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Brush Robert M.
Trimmings John P
Xilinx , Inc.
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