Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-03-01
2002-10-15
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06467057
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a scan driver of liquid crystal display (LCD), and particularly relates to a scan driver of liquid crystal display with fault detection and correction function.
2. Description of the Prior Art
In fabricating LCD (Liquid Crystal Display) panel, the TFT (Thin Film Transistor) are frequently utilized, and the LTPS (Low Temperature Polycrystalline Silicon) technology is employed to fabricate the TFT in the lately technology. Usually, in the LTPS process, the scan driver is fabricated on the glass substrate, on which the, TFT LCD is fabricated. However, the yield of the processes fabricating the scan driver is not stable, so the redundant scan driver shift register is necessary for the LCD. The fault detection and correction circuit of the shift register of the scan driver mentioned above is used to avoid the scan driver failure due to any failure of scan driver shift register.
In the prior art, all the fault detection and correction circuits are fabricated on a single side of a glass substrate. In other words, the scan driver on the glass substrate is fabricated on a single side (left or right). Even though the scan drivers are fabricated on both sides (left and right) of the glass substrate in a temp to simultaneously drive the gate buses of the TFT array, the prior art still can not drive the gate buses simultaneously from both sides. The purpose of the present invention is to propose the circuit for fault detection and correction such that the gate buses can be driven from a single side or simultaneously from both sides of the transparent (such as glass) substrate.
In the traditional TFT LCD, the mobility of the carrier in the amorphous silicon utilized to fabricate the TFT on the panel is lower than that in the crystal silicon utilized in the normal semiconductor device. So the process utilizing amorphous silicon can be used to fabricate the thin film transistor (TFT) on the panel as switches only. The process mentioned above can not be used to fabricate the transistor in the data driver or the scan driver. Thus, the scan driver and the data driver can only be fabricated in the integrated circuit using silicon as substrate instead of using glass panel. The configuration of the TFT LCD is shown in
FIG. 1
, in which the panel
10
is made of glass, and the TFT array is fabricated on the panel
10
. The scan driver integrated circuit
11
and the data driver integrated circuit
12
are both utilized to drive the transistor in the TFT array. The TFT array mentioned above includes many transistors (TFT)
14
, each connecting a transparent electrode
16
. In the prior art shown in
FIG. 1
, since the scan driver
11
and the data driver
12
are fabricated on the substrate other than the glass substrate, they must be attached to the panel
10
. The assembly takes additional effort and costs.
As the technology proceeds, the low temperature polycrystalline silicon (LTPS) technology is developed to fabricate the TFT LCD, and the polycrystalline silicon can be used to fabricate the transistors for not only switches in pixels but also scan driver circuit as well as in the data driver circuit. In other words, by using the LTPS technology, the scan driver and the data driver can be fabricated on the same panel (glass substrate) of the LCD such that the cost of the LCD is reduced. The configuration of the LCD mentioned above is shown as
FIG. 2
, in which the panel
20
is made of glass, and the TFT array is fabricated on the panel
20
. The scan driver
21
and the data driver
22
are utilized to drive the TFT array. The TFT array mentioned above includes many transistors (TFT)
24
, each connecting a transparent electrode
26
. In the prior art shown in
FIG. 2
, the scan driver
21
and the data driver
22
are fabricated on the panel (glass substrate)
20
. As shown in
FIG. 2
, the scan driver
21
is at one side of the panel
20
and is used to sequentially drive each gate bus connecting to the gate of each thin film transistor. Because only one set of scan driver is provided on the panel, any fault on the scan driver may degrade the panel and affect the yield rate.
In order to literally utilize the fault detection and correction circuit in the scan driver, and to rapidly drive the gate buses on the panel, a configuration with scan driver at both sides of the panel is provided. As shown in
FIG. 3
, the TFT array is fabricated on the panel
30
, which is made of glass. The scan driver integrated circuit
31
and the data driver integrated circuit
32
are both utilized to drive the transistors in the TFT array. The TFT array mentioned above includes many transistors (TFT)
34
, each connecting a transparent electrode
36
. In the prior art shown in
FIG. 3
, the scan driver integrated circuit
31
and the data driver integrated circuit
32
are fabricated on the panel (glass substrate)
30
, and the scan driver
31
is fabricated on both sides of the panel (glass substrate)
30
. Because the scan driver
31
at both sides of the panel can drive the gate bus, it is easier to drive the transistors on each gate bus.
The circuit diagram of the scan driver shown in
FIG. 1
,
FIG. 2
, and
FIG. 3
is a traditional one that composed of serial connected D-type flip flops (D-type FF:DFF), which is shown in FIG.
4
A. The input terminal IN is coupled to the first D-type FF Q
1
, in addition, the terminal CK provides the clock pulse to the first D-type FF Q
1
, the second D-type FF Q
2
, and third D-type FF Q
3
. . . etc. The waveform of the signal on the input terminal IN, the terminal CK, the output of the first D-type FF Q
1
, the second D-type FF Q
2
, and the third D-type FF Q
3
are shown in FIG.
4
B. Because of the pulse on each output terminal of the shift registers, all the transistors (TFT) on the scan bus are activated (on).
When the LTPS process is utilized to fabricate the shift register of the scan driver integrated circuit, the resulted shift register often fail, and thus the stuck-at-zero fault or the stuck-atone fault of the output of the shift register is frequently resulted. To solve this problem, three identical shift registers are fabricated instead of one shift register, and the majority of the output of the three identical shift registers is taken to represent the output of all the shift registers. The other method employed to solve the foregoing issue is to utilize laser to cut off and thus block the failed region. This is usually used in the one-side-driving-model LCD, i.e., the scan driver fabricated on only one side of the panel of the LCD, such as that shown in FIG.
2
.
At the beginning of developing LCD manufacturing technology, in order to overcome the issue of low yield, usually, an “OR” gate is connected to three sets of serial connected D-type FFs. The OR gate mentioned above is used to transmit the correct signal to the following sets of serial connected D-type FFs. As shown in
FIG. 5A
, it is clear that when a stuck-at-zero fault happened in any set of the serial connected D-type FFs, the correct signal (logic one or logic zero) can be transmitted to the following sets of serial connected D-type FFs, even there is only one set of serial connected D-type FF works properly. On the other hand, when there is a stuck-at-one fault happened in a set of the serial connected D-type FFs, the output of the OR gate
40
will stuck at logic one too. When the phenomenon happened, an detection is made through the test pad to find out which output(s) of the set of the serial connected D-type FFs is stuck at logic one. After finding which set of serial connected D-type FFs is stuck at one, e.g., the set of serial connected D-type FFs
41
is stuck at one, laser is utilized to cut off the output of the set of serial connected D-type FFs
41
. For example, the laser can focus at point P
1
to cut off the set of serial connected D-type FFs
41
. So the input of the OR gate
40
which stuck at logic one is prevent from connecting to the OR gate
40
, and the “floating” phenomenon will not happen
Chen Shang-Li
Wang Bo-Wen
Chung Phung M.
Industrial Technology Research Institute
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