Scalable architecture based on single-chip multiprocessing

Details Scalable architecture based on single-chip multiprocessing Scalable architecture based on single-chip multiprocessing

2006-01-17

2006-01-17

Elmore, Stephen C. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S117000, C711S118000, C711S119000, C711S127000, C711S130000, C711S141000, C711S142000, C711S145000, C711S146000, C711S147000, C711S150000, C711S157000, C370S295000, C370S351000, C370S356000, C370S395500, C709S213000, C709S214000, C709S216000, C365S230030, C365S230040, C365S230050

Reexamination Certificate

active

06988170

ABSTRACT:
A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads. A showcase example of the chip-multiprocessing system, called the PIRAHNA™ system, is a highly integrated processing node with eight simpler ALPHA™ processor cores. A method for scalable chip-multiprocessing is also provided.

REFERENCES:
patent: 5386547 (1995-01-01), Jouppi
patent: 5440752 (1995-08-01), Lentz et al.
patent: 5457679 (1995-10-01), Eng et al.
patent: 5634110 (1997-05-01), Laudon et al.
patent: 5778437 (1998-07-01), Baylor et al.
patent: 5895487 (1999-04-01), Boyd et al.
patent: 6202127 (2001-03-01), Dean et al.
patent: 6263405 (2001-07-01), Irie et al.
patent: 6295598 (2001-09-01), Beroni et al.
patent: 6457100 (2002-09-01), Ignatowski et al.
patent: 6516391 (2003-02-01), Tsushima et al.
patent: 6668308 (2003-12-01), Barroso et al.
Agrawal, Anant, et al., “An Evaluation of Directory Schemes for Cache Coherence”, Proceedings of 15th International Symposium on Computer Architecture (“ISCA”) (May 1998) pp. 280-289.
Barroso, Luiz Andre, et al., “Impact of Chip-Level Integration on Performance of OLTP Workloads”, High-Performance Computer Architecture (“HPCA”) (Jan. 2000).
Barroso, Luiz Andre, et al., “Memory System Characterization of Commercial Workloads”, ISCA (Jun. 1998).
Eggers, Susan J., et al., “Simulation Multithreading: a Platform for Next-generation Processors”, University of Washington, DEC Western Research Laboratory ((eggers.levyjlo)@cs.washington.edu) ((emer.stamm)@vssad.enet.dec.com) pp. 1-15.
Eickemeyer, Richard J., et al., “Evaluation of Multithreaded Uniprocessors for Commercial Application Environments”, ACM (1996) (0-89791-786-3) pp. 203-213.
Gupta, Anoop, et al., “Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes”, Stanford University, Computer Systems Laboratory, pp 1-10.
Hammond, Lance, et al., “A Single-Chip Multiprocessor”, IEEE (Sep. 1997) (0018-9162).
Hammond, Lance, et al., “Data Speculation Support for a Chip Multiprocessor”, Stanford University, Computer Systems Laboratory (http://www.hydra.stanford.edu/).
Jouppi, Norman P., et al., “Tradeoffs in Two-Level On-Chip Caching”, WRL Research Report 93/3, Western Research Laboratory (WRL-Techreports@decwri.dec.com) (Dec. 1993) pp. 1-31.
Krishnan, Venkata, et al., “Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-Multiprocessor”, University of Illinois at Urbana-Champaign (http://iacoma.cs.uluc.edu).
Kuskin, Jeffrey, et al., “The Stanford FLASH Multiprocessor”, Stanford University, Computer Systems Laboratory.
Laudon, James, et al., “The SGI Origin: a ccNUMA Highly Scalable Server”, Silicon Graphics, Inc. (laudon@sgl.com).
Lenoski, Daniel et al., “The Directory-Based Cache Coherence Protcol for the DASH Multiprocessor”, IEEE (1990) (CH2887-8) pp. 148-159.
Nayfeh, Basem A., et al., “Evaluation of Design Alternatives for a Multiprocessor Microprocessor”, ACM (1996) (0-89791-786-3) pp. 67-77.
Nowatzyk, Andreas G., et al., “S-Connect: from Networks of Workstations to Supercomputer Performance”, 22nd Annual International Symposium on Computer Architecture (“ISCA”) (Jun. 1995).
Nowatzyk, Andreas, et al., “Exploiting Parallelism in Cache Coherency Protocol Engines”, Sun Microsystems Computer Corporation.
Olukotun, Kunle, et al., “The Case of a Single-Chip Multiprocessor”, Proceedings Seventh International Symposium Architectural Support for Programming Languages and Operating Systems (“ASPLOS VII”) (Oct. 1996).
Steffan, J. Gregory, et al., “The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization”, HPCA-4 (Feb. 1998) pp. 1-12.
Tremblay, Marc, “MAJC-TM-5200 AVLIW Convergent MPSOC”, Sun Microsystems, Inc., Microprocessor Forum (1999).
Kunkel, Steven, et al., System Optimization for OLTP Workloads, IEEE (1999) (0272-1732) pp. 56-64.
Diefendorff, Keith, “Power4 Focuses on Memory Bandwidth”, Microdesign Resources, Microprocessor Report vol 13 No. 13, Oct. 6, 1999.
Hammond, Lance, et al., “The Stanford Hydra CMP”, Stanford University, Computer Systems Laboratory (http://www-hydra.stanford.edu).

Affiliated with

Also associated with

Rating

Scalable architecture based on single-chip multiprocessing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scalable architecture based on single-chip multiprocessing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scalable architecture based on single-chip multiprocessing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3554894