High voltage and low on-resistance LDMOS transistor having...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S335000

Reexamination Certificate

active

07102194

ABSTRACT:
A high voltage LDMOS transistor according to the present invention includes at least one P-field block in the extended drain region of the N-well. The P-field blocks form junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The source region and P-field blocks enclose the drain region, which makes the LDMOS transistor self-isolated.

REFERENCES:
patent: 6593621 (2003-07-01), Tsuchiko et al.
patent: 2001/0053581 (2001-12-01), Mosher et al.

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