Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1996-08-27
2003-07-29
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S624000, C438S788000, C438S789000
Reexamination Certificate
active
06599847
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to dielectric layers within integrated circuits. More particularly, the present invention relates to sandwich composite dielectric layer constructions which yield improved electrical circuit device reliability within integrated circuits.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
Within advanced integrated circuits having formed therein narrow linewidth electrical circuit elements and patterned layers, such as but not limited to patterned conductor layers, which define narrow pitch and high aspect ratio apertures, it has become increasingly important within those advanced integrated circuits to form dielectric layers, such as but not limited to inter-metal dielectric (IMD) layers, which possess superior gap filling and moisture impermeability characteristics in order to efficiently fill the narrow pitch and high aspect ratio apertures within those integrated circuits while simultaneously providing a diffusion barrier to moisture which might otherwise compromise the functionality and reliability of electrical circuit elements which are formed within those integrated circuits. With respect to dielectric layers which possess such superior gap filling and moisture impermeability characteristics, sandwich composite dielectric layer constructions which employ a gap filling dielectric layer sandwiched between a pair of conformal dielectric layers have received continuing interest and attention. A common sandwich composite dielectric layer construction which exhibits superior gap filling and moisture impermeability characteristics employs a lower lying conformal dielectric layer and an upper lying conformal dielectric layer formed from a silicon oxide dielectric material deposited through a plasma enhanced chemical vapor deposition (PECVD) method employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material, with plasma reactor parameters typically optimized inhibit moisture permeation through the lower lying conformal dielectric layer and upper lying conformal dielectric layer. Within such a sandwich composite dielectric layer construction, the lower lying conformal dielectric layer and the upper lying conformal dielectric layer sandwich a middle gap filling dielectric layer typically formed of either a spin-on-glass (SOG) silicon oxide dielectric layer or an ozone assisted atmospheric pressure chemical vapor deposited (APCVD) silicon oxide dielectric layer. Typically, the upper lying conformal dielectric layer within the gap filling sandwich composite dielectric layer construction so formed is subsequently planarized through a chemical mechanical polish (CMP) planarizing method, as is common in the art, to form a gap filling and planarizing sandwich composite dielectric layer construction.
While the gap filling sandwich composite dielectric layer constructions or gap filling and planarizing sandwich composite dielectric layer constructions formed through the two permutations of the foregoing conformal dielectric layers and gap filling dielectric layers are known in the art to form gap filling sandwich composite dielectric layer constructions or gap filling and planarizing sandwich composite dielectric layer constructions which may be employed as dielectric layers, including but not limited to inter-metal dielectric (IMD) layers, within integrated circuits having narrow pitch and high aspect ratio apertures defined by narrow linewidth electrical circuit elements and/or patterned layers formed therein, the gap filling sandwich composite dielectric layer constructions or gap filling and planarizing sandwich composite dielectric layer constructions formed through the two permutations of the foregoing conformal dielectric layers and gap filling dielectric layers are not without problems. In that regard, it becomes increasingly important within advanced integrated circuits within which there are formed electrical circuit elements and patterned layers, such as but not limited to patterned conductor layers, of increasingly narrower linewidth dimension which define narrow pitch and high aspect ratio apertures, to form gap filling sandwich composite dielectric layer constructions or gap filling and planarizing sandwich composite dielectric layer constructions in a fashion such that those electrical circuit elements and patterned layers of diminished linewidth dimension continue to be adequately protected from moisture permeation while simultaneously not being damaged through the plasma enhanced chemical vapor deposition (PECVD) method through which is formed the gap filling sandwich composite dielectric layer construction or gap filling and planarizing sandwich composite dielectric layer construction. It is towards that goal that the present invention is generally directed.
With regard to protection from moisture permeation through gap filling and planarizing sandwich composite dielectric layer constructions of narrow linewidth electrical circuit elements and patterned layers, there has been disclosed in the art gap filling and planarizing sandwich composite dielectric layer constructions formed from layers with enhanced crack resistance. See, for example, Matsuura, U.S. Pat. No. 5,459,105. With regard, in general, to limiting damage to electrical circuit elements and patterned layers upon which are formed plasma enhanced chemical vapor deposited (PECVD) dielectric layers within integrated circuits, it is generally understood in the art that electrical circuit elements and patterned layers of narrower dimensions are more susceptible to electrostatically and electrodynamically plasma induced damage due to: (1) a limited ability of electrical circuit elements and patterned layers of narrower dimension to store charges; and (2) an enhanced ability to discharge such charges across narrow dielectric dimensions.
It is therefore desirable in the art to form upon electrical circuit elements and patterned layers having a narrow linewidth, a narrow aperture width and a high aspect ratio, within integrated circuits, gap filling sandwich composite dielectric layer constructions or gap filling and planarizing sandwich composite dielectric layer constructions without damaging those electrical circuit elements and patterned layers, while simultaneously providing gap filling sandwich composite dielectric layer constructions or gap filling and planarizing sandwich composite dielectric layer constructions with optimal moisture impermeability. It is towards these goals that the present invention is specifically directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming for use within an integrated circuit a gap filling sandwich composite dielectric layer construction.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where when forming the gap filling and planarizing sandwich composite dielectric layer construction there is not sustained plasma damage by electrical circuit elements and patterned layers formed beneath the gap filling sandwich composite dielectric layer construction.
A third object of the present invention is to provide a method in accord with the first object of the present invention, where the gap filling sandwich composite dielectric layer construction provides optimal moisture impermeability to electrical circuit elements and patterned layers formed beneath the gap filling sandwich composite dielectric layer construction.
A fourth object of the present invention is to provide a method in accord with the second object of the present invention and the third object of the present invention, which method is
Jang Syun-Ming
Yu Chen-Hua
Ackerman Stephen B.
Jr. Carl Whitehead
Nguyen Thanh
Saile George O.
Taiwan Semiconductor Manufacturing Company
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