Sacrificial TiN arc layer for increased pad etch throughput

Details Sacrificial TiN arc layer for increased pad etch throughput Sacrificial TiN arc layer for increased pad etch throughput

2006-07-04

2006-07-04

Nguyen, Thanh (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S669000, C438S672000, C438S685000

Reexamination Certificate

active

07071101

ABSTRACT:
A method of manufacturing a semiconductor device wherein a final layer of metal is formed on a layer of interlayer dielectric, forming a layer of TiN on the final layer of metal, forming a layer of photoresist on the layer of TiN, patterning and developing the layer of photoresist exposing portions of the final metal layer, and etching the exposed portions of the final metal layer forming metal structures. The layer of photoresist and layer of TiN are removed. A blanket layer of interlayer dielectric is formed on the surface of the semiconductor device. A second layer of photoresist is formed on the blanket layer of interlayer dielectric. The second layer of photoresist is patterned and developed exposing portions of the interlayer dielectric overlying the metal structures. The exposed portions of the interlayer dielectric are etched down to the surface of the metal structures.

REFERENCES:
patent: 5741626 (1998-04-01), Jain et al.
patent: 5880026 (1999-03-01), Xing et al.
patent: 5882999 (1999-03-01), Anderson et al.
patent: 5920790 (1999-07-01), Wetzel et al.

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