Sacrificial dielectric planarization layer

Details Sacrificial dielectric planarization layer Sacrificial dielectric planarization layer

2005-06-21

2005-06-21

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S680000

Reexamination Certificate

active

06908863

ABSTRACT:
A method of forming a microelectronic structure and its associated structures is described. In one embodiment, a substrate is provided with a sacrificial layer disposed on a hard mask layer, and a metal layer disposed in a trench of the substrate and on the sacrificial layer. The metal layer is then removed at a first removal rate wherein a dishing is induced on a top surface of the metal layer until the sacrificial layer is exposed, and simultaneously removing the metal layer and the sacrificial layer at a second removal rate without substantially removing the hard mask.

REFERENCES:
patent: 6287961 (2001-09-01), Liu et al.
patent: 6297554 (2001-10-01), Lin
patent: 6326300 (2001-12-01), Liu et al.
patent: 6472306 (2002-10-01), Lee et al.
patent: 6576551 (2003-06-01), Chang et al.

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