Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-08-27
2001-03-06
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S627000, C438S643000, C438S653000, C257S486000, C257S740000, C257S741000, C257S757000
Reexamination Certificate
active
06197628
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and the fabrication thereof. More particularly, the present invention pertains to diffusion barrier layers.
BACKGROUND OF THE INVENTION
In the fabrication of integrated circuits, various conductive layers are used. For example, during the formation of semiconductor devices, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), ferroelectric (FE) memories, etc., conductive materials are used in the formation of storage cell capacitors and also may be used in interconnection structures, e.g., conductive layers in contact holes, vias, etc. In many applications, it is preferable that the materials used provide effective diffusion barrier characteristics.
For example, effective diffusion barrier characteristics are required for conductive materials used in the formation of storage cell capacitors of memory devices, e.g., DRAMs. As memory devices become more dense, it is necessary to decrease the size of circuit components forming such devices. One way to retain storage capacity of storage cell capacitors of the memory devices and at the same time decrease the memory device size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. Therefore, high dielectric constant materials are used in such applications interposed between two electrodes. One or more layers of various conductive materials may be used as the electrode material. However, generally, one or more of the layers of the conductive materials used for the electrodes (particularly the bottom electrode of a cell capacitor) must have certain diffusion barrier properties, e.g., silicon diffusion barrier properties. Such properties are particularly required when high dielectric constant materials are used for the dielectric layer of the storage cell capacitor because of the processes used for forming such high dielectric materials, e.g., deposition of high dielectric materials usually occurs at high temperatures (generally greater than about 500° C.) in an oxygen-containing atmosphere.
Generally, various metals and metallic compounds, for example, metals such as platinum, and conductive metal oxides, such as ruthenium oxide, have been proposed as the electrodes or at least one of the layers of an electrode stack for use with high dielectric constant materials. However, reliable electrical connections should generally be constructed which do not diminish the beneficial properties of the high dielectric constant materials. For platinum or ruthenium oxide to function well as a bottom electrode or as one of the layers of an electrode stack, an effective barrier to the diffusion of silicon from the substrate or other silicon containing region to the top of the electrode needs to be provided. This is required since silicon at the surface of the electrode stack will tend to be oxidized during the oxygen anneal of the high dielectric constant materials, e.g, Ta
2
O
5
or BaSrTiO
3
, which will result in a decreased series capacitance, thus degrading the storage capacity of the cell capacitor.
Platinum and ruthenium oxide, used alone as an electrode, are generally too permeable to silicon to be used as a bottom electrode of a storage cell capacitor formed on a silicon substrate region. Because of the permeability of such materials to silicon, typically platinum is used as a layer in an electrode stack which acts as the electrode as well as a diffusion barrier for integration of capacitors directly formed on silicon. For example, as described in the article “Novel High Temperature Multilayer Electrode-Barrier Structure for High Density Ferroelectric Memories” by H. D. Bhatt, et al.,
Appl. Phys. Letter,
71(5), Aug. 4, 1997, the electrode barrier structure includes layers of platinum: rhodium alloy, in addition to platinum: rhodium oxide layers, to form electrodes with diffusion barrier properties. Such alloy layers are formed using physical vapor deposition (PVD) processing, e.g., reactive RF sputtering processes. Further, for example, the article entitled “(Ba, Sr)TiO
3
Films Prepared by Liquid Source Chemical Vapor Deposition on Ru Electrodes” by Kawahara et al.,
Jpn.J.Appl.Phys.
, Vol. 35 (1996) Pt. 1, No. 9B, pp. 4880-4885, describes the use of ruthenium and ruthenium oxide for forming electrodes in conjunction with high dielectric constant materials.
Many storage cell capacitors are fabricated which include electrode layers that are formed by deposition of a conductive material within a small high aspect ratio opening. Typically, sputtering does not provide a sufficiently conformal layer adequate for formation of an electrode layer within such a small high aspect ratio opening.
In addition to the formation of capacitor electrodes, the formation of barrier layers for use in other applications, e.g., interconnect applications, is also desirable. For example, diffusion barriers are commonly used to prevent undesirable reactions in contact openings.
SUMMARY OF THE INVENTION
To overcome the problems described above, RuSi
x
diffusion barrier layers, along with structures incorporating such diffusion barrier layers and methods associated therewith, are described herein.
A method for use in the fabrication of integrated circuits according to the present invention includes providing a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion barrier layer is formed of RuSi
x
, where x is in the range of about 0.01 to about 10.
In one embodiment of the method, the diffusion barrier layer is formed of RuSi
x
, where x is in the range of about 1 to about 3, more preferably about 2.
In another embodiment of the method, the barrier layer is formed by depositing RuSi
x
by chemical vapor deposition. In an alternative embodiment, the barrier layer is formed by forming a layer of ruthenium relative to a silicon containing region and performing an anneal to form RuSi
x
from the layer of ruthenium and the silicon containing region.
A method for use in the formation of a capacitor according to the present invention includes forming a first electrode on a portion of a substrate assembly. A high dielectric material is formed over at least a portion of the first electrode and a second electrode is formed over the high dielectric material. At least one of the first and second electrodes includes a barrier layer formed of RuSi
x
, where x is in the range of about 0.01 to about 10.
Another method according to the present invention for use in the formation of a capacitor includes providing a silicon containing region of a substrate assembly. A first electrode is formed on at least a portion of the silicon containing region of the substrate assembly. The first electrode includes a barrier layer of RuSi
x
, where x is in the range of about 0.01 to about 10. A high dielectric material is formed over at least a portion of the first electrode and a second electrode is provided over the high dielectric material.
In one embodiment of the method, the formation of the barrier layer includes forming a layer of ruthenium on at least a portion of the silicon containing region. Thereafter, the layer of ruthenium formed on the at least a portion of the silicon containing region is annealed resulting in the RuSi
x
barrier layer. The layer of ruthenium may be deposited by chemical vapor deposition with a thickness of about 10 Å to about 300 Å.
In another embodiment of the method, one or more conductive layers are formed relative to the RuSi
x
barrier layer. The one or more conductive layers are formed of at least one of a metal or a conductive metal oxide, e.g., formed from materials selected from the group of RuO
2
, RhO
2
, MoO
2
, IrO
2
, Ru, Rh, Pd, Pt, and Ir.
A semiconductor device structure according to the present invention includes a substrate assembly including a surface and a diffusion barrier layer over at least a portion of the surface. The diffusion barrier layer is formed of RuSi
x
, where x is in the range of about 0.01 to
Marsh Eugene P.
Vaartstra Brian A.
Lee Granvill
Micro)n Technology, Inc.
Mueting Raasch & Gebhardt, P.A.
Smith Matthew
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