Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-10-18
2005-10-18
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S204000, C711S213000, C712S207000, C712S230000
Reexamination Certificate
active
06957304
ABSTRACT:
A method and apparatus are described for protecting cache lines allocated to a cache by a run-ahead prefetcher from premature eviction, preventing thrashing. The invention also prevents premature eviction of cache lines still in use, such as lines allocated by the run-ahead prefetcher but not yet referenced by normal execution. A protection bit indicates whether its associated cache line has protected status in the cache or whether it may be evicted.
REFERENCES:
patent: 5920889 (1999-07-01), Petrick et al.
patent: 5983324 (1999-11-01), Ukai et al.
Microsoft Computer Dictionary, 1999, Microsoft Press, Fourth Edition, p. 111.
Dundas, J., et al., “Improving Data Cache Performance by Pre-executing Instructions Under a Cache Miss”,Proceedings of the 1997 International Conference on Supercomputing, 68-75, (1997).
Inoa Midys
Intel Corporation
Padmanabhan Mano
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Runahead allocation protection (RAP) does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Runahead allocation protection (RAP), we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Runahead allocation protection (RAP) will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3478654