Programmable direct interpolating delay locked loop

Details Programmable direct interpolating delay locked loop Programmable direct interpolating delay locked loop

2005-10-25

2005-10-25

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S261000

Reexamination Certificate

active

06958634

ABSTRACT:
Embodiments of the invention provide for a delay locked loop architecture including a coarse-fine type arrangement using one loop for non-continuous strobe that can be also be configured for continuous clocks as well. In particular, a reference loop establishes precise coarse unit delay. A slave delay line duplicates unit delay. A phase interpolator interpolates between unit delay to produce fine delay.

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patent: 2003/0042957 (2003-03-01), Tamura
PCT International Search Report dated May 6, 2005—related application, International Application No. PCT/US2004/043664—International Filing Date Dec. 22, 2004 (14 pages).
“Programmable Memory Controller”, IBM Technical Disclosure Bulletin, IBM Corp., New York, USA, vol. 31, No. 9, Feb. 1, 1989, pp. 351-354, XP000097564, ISSN: 0018-8689.
Patent Abstracts of Japan, vol. 1999, No. 14, Dec. 22, 1999 and JP 11 261408, Inventor: Wakayama Shigetoshi, Applicant: Fujitsu Ltd., entitled “Phase Interpolator, Timing Signal Generating Circuit, and Semiconductor Integrated Circuit Device and Semiconductor Integrated Circuit System Adopting the Timing Signal Generating Circuit”.
EP 1 229 646 A2, Date of Publication Aug. 7, 2002, Inventor: Tanahashi, Toshio, Applicant: NEC Corporation, entitled “Two Step Variable Length Delay Circuit”.
JP 2000 298532 A (Hitachi Ltd; Hitachi ULSI Systems Co. Ltd.), Oct. 24, 2000.

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