Rugged polysilicon process for DRAM capacitors

Details Rugged polysilicon process for DRAM capacitors Rugged polysilicon process for DRAM capacitors

1997-02-26

1998-11-17

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, 438964, H01L 288242

Patent

active

058375791

ABSTRACT:
A stacked capacitor DRAM is formed on a substrate having a pass transistor and a wiring line covered by a layer of insulator. A self-aligned contact process is used to expose the surface of one of the source/drain regions of the pass transistor and three layer stack is deposited over the layer of insulator. The lowest, first layer is polysilicon in contact with the one source/drain region of the pass transistor, the second layer is silicon oxide, and the third, topmost layer of the stack is either silicon nitride or polysilicon. A mask is formed over the third layer to laterally define the capacitor structure and then the third and second layers are etched down to the surface of the first, polysilicon layer. Differential etching is then performed to laterally etch the second layer without etching the first or third layers. The mask is removed and hemispherical grained silicon (HSG-Si) is grown over all of the exposed surfaces of the device. The first layer is then etched using conventional photolithography to finish defining the lateral extent of the lower capacitor electrode, then a capacitor dielectric layer and an upper capacitor electrode are provided.

REFERENCES:
patent: 5049517 (1991-09-01), Liu et al.
patent: 5278091 (1994-01-01), Fazan et al.
patent: 5597754 (1997-01-01), Lou et al.
patent: 5618747 (1997-04-01), Lou

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