RTL power analysis using gate-level cell power models

Details RTL power analysis using gate-level cell power models RTL power analysis using gate-level cell power models

2005-05-31

2005-05-31

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C703S018000

Reexamination Certificate

active

06901565

ABSTRACT:
A system for analyzing the power consumption of a behavior description of an electrical design includes a structural element library including a set of technology-independent structural macro elements, a macro power model module providing macro power models for one or more of the structural macro elements in the structural element library, and a power estimation module providing a power consumption value of the electrical design using a netlist of interconnected components representative of the electrical design, and the macro power models. The macro power models are associated with corresponding power models in a user-specified gate-level power model library. The power analysis system enables behavior level or RTL power analysis using a user-specified gate-level cell power model library containing arc-based or pin-based power model descriptions or both.

REFERENCES:
patent: 5719800 (1998-02-01), Mittal et al.
patent: 6212665 (2001-04-01), Zarkesh et al.
patent: 6367023 (2002-04-01), Kling et al.
patent: 6598209 (2003-07-01), Sokolov

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