Isolation techniques for reducing dark current in CMOS image...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

Reexamination Certificate

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C257S513000, C257S524000, C257S508000, C257S760000, C257S222000, C257S225000, C257S223000, C257S330000

Reexamination Certificate

active

06888214

ABSTRACT:
Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench.

REFERENCES:
patent: 6118142 (2000-09-01), Chen et al.
patent: 6177333 (2001-01-01), Rhodes
patent: 6204524 (2001-03-01), Rhodes
patent: 6232626 (2001-05-01), Rhodes
patent: 6501149 (2002-12-01), Hong
patent: 6545302 (2003-04-01), Han
patent: 6548861 (2003-04-01), Palm et al.
patent: 6555891 (2003-04-01), Furukawa et al.
R. H. Nixon, et al.—“256 × 256 CMOS Active Pixel Sensor Camer-on-a-Chip,” IEEE Journal of Solid State Circuits, vol. 31, No. 12, Dec. 1996, pp. 2046-2050.
Sunetra Mendis, et al.—“ CMOS Active Pixel Image Sensor,” IEEE Transactions on Electron Devices, vol. 41, No. 3, Mar. 1994, pp. 452-453.

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