Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-06-16
2000-05-16
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438954, 438786, H01L 21336, H01L 2131, H01L 21469
Patent
active
060636661
ABSTRACT:
In one embodiment, the present invention relates to a method of forming a flash memory cell involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer, wherein the second oxide layer is made by forming the second oxide layer by rapid thermal chemical vapor deposition at a temperature from about 780.degree. C. to about 820.degree. C. using SiH.sub.4 and N.sub.2 O and annealing in an N.sub.2 O atmosphere a temperature from about 980.degree. C. to about 1020.degree. C.; forming a second polysilicon layer over the insulating layer; etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, wherein the source region and the drain region are self-aligned by the stacked gate structure, thereby forming at least one memory cell.
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Olivo, P., Z.A. Weinberg, K.J. Stein and D.S. Wen, "Charge Trapping And Retention In Ultra-Thin Oxide-Nitride-Oxide Structures", Solid State Electronics, vol. 34, No. 6, pp. 609-611, 1991 no month.
Chang Kent Kuohua
Chi David
Advanced Micro Devices , Inc.
Ghyka Alexander G.
Niebling John F.
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