RRAM memory timing learning tool

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000

Reexamination Certificate

active

11000104

ABSTRACT:
A method of generating a timing model for a customer memory configuration, by generating a plurality of template memory netlists for a given RRAM design. Timing models for the template memory netlists are produced and stored in a first database. The template memory netlists are stored in a second database. A netlist for the customer memory configuration is generated and compared to the template memory netlists to find a match. When a match is found, one of the timing models that is associated with the matching template memory netlist is used as the timing model for the customer memory configuration. When a match is not found, two of the template memory netlists that bound the customer netlist are found, according to at least one parameter, and the timing model for the customer memory configuration is interpolated based on the two bounding template memory netlists.

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patent: 7089512 (2006-08-01), Iadanza et al.
patent: 2006/0107247 (2006-05-01), Andreev et al.
patent: 2006/0117281 (2006-06-01), Nikitin et al.

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