Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-11-02
2002-05-14
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030
Reexamination Certificate
active
06388925
ABSTRACT:
BACKGROUND OF THE INVENTION
In general, integrated circuit memory and merged memory with logic (MML) (sometimes referred to herein as semiconductor memory devices) include redundancy circuits for replacing defective memory cells. In general, redundancy circuits include redundant memory cells, which replace defective memory cells, and a redundant selection circuit for selecting the redundant memory cell. The redundant selection circuit typically includes fuses, which a laser can cut, and generates a redundancy signal for accessing the redundant memory cells in response to input of an address of a defective memory cell.
FIG. 1
is a block diagram of a semiconductor memory device employing a conventional row redundancy scheme. In
FIG. 1
, the semiconductor memory device includes: memory blocks
11
a
and
11
b
including sections
11
a
1
and
11
b
1
containing normal memory cells and sections
11
a
2
and
11
b
2
containing redundant memory cells: row decoders
12
a
and
12
b
for respective memory blocks
11
a
and
11
b
; redundant selection circuits
13
a
and
13
b
; block selection signal generators
14
a
and
14
b
; and block control circuits
15
a
and
15
b
. Each memory block
11
a
or
11
b
can be a separate memory array or bank having associated circuits such as block control circuit
15
a
or
15
b
that operate independently of the other memory blocks
11
b
or
11
a.
When a memory cell in normal memory section
11
a
1
or
11
b
1
is defective, the defective memory cell can be replaced only by a redundant memory cell in the redundant memory section
11
a
2
or
11
b
2
included in the same memory block
11
a
or
11
b
. For example, when a memory cell M in the normal memory section
11
a
1
is defective, a row of memory cells including a wordline WL connected to the defective memory cell M can be replaced only by a row of redundant memory cells in the redundant memory section
11
a
2
. When a memory cell in the normal memory section
11
b
1
is defective, the wordline connected to the defective memory cell, that is, a defective wordline in the normal memory section
11
b
1
, can be replaced only by a redundant wordline in the redundant memory section
11
b
2
.
Accordingly in the device of
FIG. 1
, when the number of defective wordlines in a normal section is larger than the number of redundant wordlines in the associated redundant memory section, the memory device cannot be repaired. For example, if the number of defective wordlines in the normal memory section
11
a
1
is larger than the number of redundant wordlines in the redundant memory section
11
a
2
, the redundant wordlines cannot replace all of the defective wordlines even though the other redundant memory sections, for example, the redundant memory section
11
b
2
, may contain available redundant wordlines. Such devices are unrepairable and must be discarded, which reduces manufacturing yield of operable memory devices.
SUMMARY OF THE INVENTION
To solve the above problem, the present invention provides a semiconductor device having a row redundancy scheme capable or promoting redundancy efficiency. In particular, a redundancy scheme in accordance with an embodiment of the invention uses redundant memory cells or row lines in one memory block (e.g., array or bank) to replace defective memory cells in another memory block (e.g., another array or bank).
According to one embodiment of the present invention, a semiconductor device includes means for replacing some defective wordlines in a normal memory section included in one memory block with redundant wordlines in a redundant memory section included in the memory block and replacing any remaining defective wordlines with redundant wordlines in a redundant memory section included in another memory block.
In an exemplary embodiment, the means comprises a plurality of redundant selection circuits, a plurality of block selection signal generators, a plurality of row decoders, and a control circuit.
Each redundant selection circuit can store a repair address corresponding to a defective wordline in any normal memory section, and each redundant selection circuit activates a redundancy signal for selecting a redundant wordline in a corresponding redundant memory section when an input address coincides with the stored repair address. The block selection signal generator activates the corresponding block selection signals in response to the most significant bits of the input address when the redundancy signals are deactivated, and each block selection signal generator activates the corresponding block selection signal regardless of the most significant address bits when a corresponding one of the redundancy signals is activated.
The row decoders select normal wordlines of a corresponding normal memory section in response to the input address when the redundancy signals are deactivated. The row decoders are disabled when one of the redundancy signals is activated.
The control circuit is commonly connected to the block selection signal generators and the row decoders and controls the block selection signal generators and the row decoders in response to a precharge signal and/or the redundancy signals.
According to another embodiment of the present invention, a semiconductor device includes memory blocks, redundant selection circuits, block selection signal generators, row decoders, and a control circuit. A defective wordline in a normal memory section of one of the memory blocks is replaced by a redundant wordline in a redundant memory section in a memory block other than the memory block containing the defective wordline.
Each of the memory blocks includes a normal memory section and a redundant memory section and is selected in response to a corresponding block selection signal. The redundant selection circuits generate a redundancy signal for selecting a redundant wordline in a corresponding redundant memory section when an input address coincides with a repair address stored therein.
The block selection signal generators generate corresponding block selection signals in response to the most significant bits of the input address, a control signal, and a corresponding redundancy signal. The row decoders are controlled by the control signal and select normal wordlines of a corresponding normal memory section in response to the input address. The control circuit generates the control signal in response to a precharge signal and the redundancy signals.
Therefore, in a semiconductor device having a row redundancy scheme according to the present invention, the defective wordlines can be replaced even when the number of defective wordlines in a normal memory section is larger than the number of redundant wordlines in a redundant memory section in the same memory block. Accordingly, the redundancy efficiency is significantly improved.
REFERENCES:
patent: 5325334 (1994-06-01), Roh et al.
patent: 5485424 (1996-01-01), Kawamura
patent: 5841709 (1998-11-01), McClure
patent: 5978291 (1999-11-01), Kirihata
patent: 6084807 (2000-07-01), Choi
patent: 6137735 (2000-10-01), Wei et al.
patent: 793991 (1996-07-01), None
Heid David W.
Le Thong
Samsung Electronics Co,. Ltd.
LandOfFree
Row redundancy scheme capable of replacing defective... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Row redundancy scheme capable of replacing defective..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Row redundancy scheme capable of replacing defective... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2857595