Row redundancy for nonvolatile semiconductor memories

Details Row redundancy for nonvolatile semiconductor memories Row redundancy for nonvolatile semiconductor memories

1996-01-29

1997-12-16

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

36518905, 365210, 36523008, G11C 1300

Patent

active

056993064

ABSTRACT:
A redundant circuit for EEPROMs which is capable of replacing defective normal memory cells with redundant memory cells in a wafer state as well as in a packaged state. The nonvolatile semiconductor memory includes an array having normal row blocks and redundant row blocks. A normal row decoder selects one of the normal row blocks, and a normal row decoder disable circuit disables the normal row decoder in response to a redundant array selection command. A redundant row block selection circuit selects one of the redundant row blocks in response to the redundant array selection command and an external address. First and second redundant latch circuits are provided for storing programmed addresses corresponding to defective normal row blocks. The second redundant latch circuit is programmed when first redundant row blocks are defective, and is capable of being programmed in a package state. Thereafter, a redundant address overlap selection prevention circuit prevents both the first and second redundant row blocks from being selected when the defective normal row block address is specified, and enables only the second redundant row block to be selected instead.

REFERENCES:
patent: 5457655 (1995-10-01), Savignac et al.
patent: 5477492 (1995-12-01), Ohsaki et al.

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