Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1993-07-13
1994-09-20
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 371 103, G11C 700
Patent
active
053495560
ABSTRACT:
The present invention discloses a row redundancy circuit in which, when the number of word lines containing defective memory cells in a first normal memory cell array is greater than the number of redundant word lines in a first redundant memory cell array, an adjacent redundant row address decoder and associated adjacent redundant word lines are used to repair such excess number of defects. Therefore, there is no need to increase the number of redundant row address decoders and redundancy efficiency is greatly increased.
REFERENCES:
patent: 4660179 (1987-04-01), Aoyama
patent: 4727516 (1988-02-01), Yoshida et al.
patent: 5255234 (1993-10-01), Seok
Popek Joseph A.
Samsung Electronics Co,. Ltd.
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