Row redundancy circuit for a semiconductor memory device

Details Row redundancy circuit for a semiconductor memory device Row redundancy circuit for a semiconductor memory device

1992-09-09

1994-08-09

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 371 101, 371 103, G11C 700

Patent

active

053372778

ABSTRACT:
A row redundancy circuit for repairing a defective cell of a memory cell array in a semiconductor memory device comprising an address selector 300 for receiving two or more of address bit pairs, of an address bit pair group, designating the defective cell to selectively output one of the two or more address bit pairs, a fuse box 100 for storing the information of the remaining address bits of the address bit pair group, except the address bits of the selected address bit pair output by the address selector, and at least a redundant decoder 200, 200A for decoding the output signals of the address selector and fuse box, thereby maximizing the row redundancy efficiency.

REFERENCES:
patent: 4342005 (1982-07-01), Harford
patent: 4464632 (1984-08-01), Yoshihisa et al.
patent: 4992984 (1991-02-01), Busch et al.

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