Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1994-11-17
1995-10-24
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 371 103, G11C 700
Patent
active
054615879
ABSTRACT:
A row redundancy circuit for use in a semiconductor memory device having one memory cell array, and first and second main row decoders and first and second spare row decoders formed on both sides of the memory cell array includes a first fuse box for receiving addresses and, during the occurrence of a defective address out of the received addresses, cutting a fuse on an input path of the defective address, thereby to supply an output signal to the first spare row decoder, a second fuse box for receiving addresses and, during the occurrence of a defective address out of the received addresses, cutting a fuse on an input path of the defective address, thereby to supply an output signal to the second spare row decoder, and a row redundancy control circuit for receiving the output signals of the first and second fuse boxes and selectively supplying an output signal responsive to the received input signal level to the first and second spare row decoders.
REFERENCES:
patent: 4837747 (1989-06-01), Dosaka et al.
patent: 4935899 (1990-06-01), Morigami
patent: 5299164 (1994-03-01), Takeuchi et al.
patent: 5359560 (1994-10-01), Suh et al.
patent: 5377146 (1994-12-01), Reddy et al.
Dinh Son
Donohoe Charles R.
Nelms David C.
Samsung Electronics Co,. Ltd.
Whitt Stephen R.
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