Static information storage and retrieval – Read/write circuit – Precharge
Patent
1980-12-24
1982-07-06
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Precharge
365190, 365233, G11C 1140
Patent
active
043386792
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention pertains to semiconductor integrated circuits and more particularly to a row driver circuit for a semiconductor memory.
BACKGROUND OF THE INVENTION
In semiconductor integrated circuit memories, both static and dynamic, memory calls are typically accessed by charging a row line which is connected to a plurality of access transistors for the memory cells. Each of the access transistors presents a capacitive loading on the row line. The row lines are typically polysilicon and offer a significant impedance to the charging signal. It can be seen that as semiconductor memories become larger more power is required to drive the row lines due to increased capacitive loading as well as the resistance of the row line itself, if the cycle time of the memory is not to be reduced.
It has typically been the approach to this problem to fabricate a bigger driver circuit with more and large transistors for handling the greater load. This, however, presents more problems since, with more dense circuits and smaller geometries, less room is available for row driver circuits. Further the larger driver circuits themselves require more powerful decoder and buffer circuits which again increases the power and area of the integrated circuit.
Therefore, in view of these problems, there exists a need for a row driver circuit for static and dynamic memories wherein the problems of capacitive loading, excessive power consumption and access time are overcome.
SUMMARY OF THE INVENTION
An illustrative embodiment of a row driver circuit of the present invention includes a row driver transistor for each of the row lines of a semiconductor memory. Each of the row driver transistors has a drain terminal, a source terminal and a gate terminal and the source terminal of each of the row driver transistors is connected to the corresponding row line. A row decoder circuit is provided for receiving a plurality of first address bits and generating therefrom a drive signal at the output terminal when the row decoder circuit is selected by the first address bits. A transition detector circuit is provided for receiving the row address bits provided to the memory and generating therefrom a transition signal having a preset duration of the active state when there is a change of state for any one of the address bits. A circuit is further provided which is responsive to the drive signal for holding at a fixed potential, ground, a group of row lines corresponding to the row line decoder. Further circuit means are provided which are responsive to the transition signal for connecting the output terminal of the row decoder to the gate terminals of the corresponding row driver transistors wherein the gate terminals of the row driver transistors are charged when the first address bits select the row decoder circuit and the active state of the transition signal is generated. The circuit then selectively isolates the charged gate terminals to permit capacitive coupling. A clock decoder circuit is connected to receive a plurality of second address bits and the transition signal for generating therefrom any one of a plurality of clock signals at the respective output terminals thereof. The output terminals of the clock decoder are respectively connected to the drain terminals of the row driver transistors for capacitively coupling the voltage on the precharged gate terminals of the corresponding row driver transistors to thereby charge the corresponding row line to at least the voltage of the clock signal.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following Description taken in conjunction with the accompanying Drawings in which:
FIG. 1 is a block and schematic illustration of a row driver circuit for use with the semiconductor memory having static memory cells, and
FIG. 2 is an illustration of selected signals which occur in the schematic diagram shown in FIG. 1.
DETAILED DESCRIPTION
Referring to FIG. 1 there
REFERENCES:
patent: 3832699 (1974-08-01), Matsue
patent: 3906461 (1975-09-01), Cappon
patent: 4204277 (1980-05-01), Kinoshita
patent: 4255679 (1981-03-01), White, Jr. et al.
patent: 4281399 (1981-07-01), Yamamoto
Fears Terrell W.
Mostek Corporation
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