Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-11-25
1999-01-12
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438270, H01L 218246
Patent
active
058588418
ABSTRACT:
A three-dimensional ROM device includes a silicon substrate having plurality of parallel trenches formed in an upper surface thereof, and a plurality of raised mesa regions. Each trench has a bottom and a pair of sidewalls, and is separated from an adjacent trench by a respective mesa region. A plurality of separated, parallel source/drain regions are provided, including a first and second source/drain region located on respective opposite sides of a respective trench bottom, and a third and fourth source/drain region located on respective opposite sides of a respective raised mesa region. Each source/drain region serves as a bit line. A gate oxide layer is located on the upper surface of the silicon substrate. A plurality of sidewall oxide layers are formed on selected sidewalls and serve as channel barriers. A plurality of silicon nitride layers are formed above selected mesa regions and trench bottoms, and serve as channel barriers. A plurality of gate layers are located over the gate oxide layer and the silicon nitride layers and serve as word lines. A region between any two adjacent source/drain regions comprises a channel region.
REFERENCES:
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5504025 (1996-04-01), Fong-Chung et al.
patent: 5627091 (1997-05-01), Hong
patent: 5744393 (1998-04-01), Risch et al.
Chaudhari Chandra
United Microelectronics Corporation
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