Communications: electrical – Condition responsive indicating system – Specific condition
Reexamination Certificate
2007-12-11
2007-12-11
Hofsass, Jeffery (Department: 2612)
Communications: electrical
Condition responsive indicating system
Specific condition
C324S765010, C324S537000, C324S754090, C324S759030, C324S763010
Reexamination Certificate
active
11014075
ABSTRACT:
Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.
REFERENCES:
patent: 4495628 (1985-01-01), Zasio
patent: 4495629 (1985-01-01), Zasio
patent: 4912709 (1990-03-01), Teske et al.
patent: 4969148 (1990-11-01), Nadeau-Dostie et al.
patent: 5003204 (1991-03-01), Cushing et al.
patent: 5053700 (1991-10-01), Parrish
patent: 5130568 (1992-07-01), Miller et al.
patent: 5254942 (1993-10-01), D'Souza et al.
patent: 5257223 (1993-10-01), Dervisoglu
patent: 5355369 (1994-10-01), Greenberger et al.
patent: 5648661 (1997-07-01), Rostoker et al.
patent: 5689517 (1997-11-01), Ruparel
patent: 5831330 (1998-11-01), Chang
patent: 6070252 (2000-05-01), Xu et al.
patent: 6104291 (2000-08-01), Beauvillier et al.
patent: 6122762 (2000-09-01), Kim
patent: 6137155 (2000-10-01), Seshan et al.
patent: 6236223 (2001-05-01), Brady et al.
patent: 6249227 (2001-06-01), Brady et al.
patent: 6357025 (2002-03-01), Tuttle
patent: 6380729 (2002-04-01), Smith
patent: 6404684 (2002-06-01), Arimoto et al.
patent: 6412086 (2002-06-01), Friedman et al.
patent: 6412786 (2002-07-01), Pan
patent: 6426904 (2002-07-01), Barth et al.
patent: 6525410 (2003-02-01), Gelsomini et al.
patent: 6563751 (2003-05-01), Wu
patent: 6566736 (2003-05-01), Ogawa et al.
patent: 6666380 (2003-12-01), Suzuya
patent: 6727722 (2004-04-01), Whetsel
patent: 6774470 (2004-08-01), Yagi et al.
patent: 6806494 (2004-10-01), Fenner et al.
patent: 6838773 (2005-01-01), Kikuchi et al.
patent: 6865701 (2005-03-01), Youngs et al.
patent: 6888365 (2005-05-01), Ma et al.
patent: 6930499 (2005-08-01), Van Arendonk et al.
patent: 6962827 (2005-11-01), Furue et al.
patent: 6982190 (2006-01-01), Roesner
patent: 7023347 (2006-04-01), Arneson et al.
patent: 7119567 (2006-10-01), Ma et al.
patent: 2002/0094596 (2002-07-01), Higuchi
patent: 2002/0094639 (2002-07-01), Reddy
patent: 2002/0125546 (2002-09-01), Muta
patent: 2005/0083203 (2005-04-01), Surkau
patent: 2005/0155213 (2005-07-01), Eastin
patent: 2005/0212674 (2005-09-01), Desmons et al.
patent: 2005/0241146 (2005-11-01), Hamburgen
patent: 2006/0038687 (2006-02-01), White et al.
patent: 2006/0125506 (2006-06-01), Hara et al.
patent: 2006/0145710 (2006-07-01), Puleston et al.
IMPINJ, Inc., Products,How RFID Works, pp. 2, printed Apr. 30, 2004, www.impinj.com/products/rfid/applications.php.
IMPINJ, Inc.,Self-Adaptive Silicon, pp. 7, printed Apr. 30, 2004, www.impinj.com/technology/index.php.
Jarwala, N.,Designing Dual Personality IEEE 1149.1 Compliant Multi-Chip Modules, 1994, IEEE International Test Conference, paper 19.3, pp. 446-455.
Oakland, S.,Considerations for Implementing IEEE 1149.1 on System-on-a-Chip Integrated Circuits, Test Conference, 2000, Proceedings International, Oct. 3-5, pp. 628-637.
Levitt, M., et al.,Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor, 1995, International Test Conference, paper 6.2, pp. 157-166.
Wood, S., et al.,A 5 GB/s 9-Port Application Specific SRAM with Built-in Self Test, 1995 International Workshop on Memory Technology, Design and Testing, Aug. 7-8, pp. 68-73.
Yurash, S., et al.,Automatic Test Pattern Generation Comes of Age, Electronic Engineering, vol. 63, No. 777, Sep. 1991, London GB, pp. 35-36 & 38.
Eichelberger, E.B., et al.,A Logic Design Structure for LSI Testability, Reprinted from the Proceedings of the 14th Design Automation Conference by the Institute of Electrical and Electroincs Engineers, Inc., pp. 206-212 (1997).
Youngs, L., et al.,Design of the UltraSPARCTM-I Microprocessor for Manufacturing performance, pp. 179-186, SPIE vol. 2874, Texas Instruments, Inc., Stafford, Texas, USA, assessed Mar. 8, 2004.
Atmel,IEEE 1149.1-1990 Standard Test Access Port Boundary Scan, 1900 IEEE Standard 1149.1, pp. 6, Sep. 1999.
Dennis Kiyoshi Hara, et al., “RFID Tag With Bist Circuits”, U.S. Appl. No. 11/014,076, filed on Dec. 15, 2004, Notice of Allowance Office Action mailed Jan. 22, 2007. The Notice of Allowance Office Action, claims as they stood in the application prior to the mailing of the Notice of Allowance Office Action and a copy of the Claims as they were presented to the PTO in response to the Notice of Allowance Office Action. Notice of Allowance Office Action mailed Jun. 28, 2007. The Notice of Allowance Office Action and a copy of the claims as allowed.
John D. Hyde, et al., “Wafer Level Testing for RFID Tags”, U.S. Appl. No. 11/014,523, filed on Dec. 15, 2004, Restriction Requirement Office Action mailed Jun. 23, 2006 and Office Action mailed Oct. 20, 2006. The Office Actions and claims as they stood in the application prior to the mailing of the Office Action and claims as presented to the PTO in response to the office actions.
Glidden Robert M.
Hara Dennis Kiyoshi
Hyde John D.
Kuhn Jay A.
Oliver Ronald A.
Blakely , Sokoloff, Taylor & Zafman LLP
Fan Hongmin
Hofsass Jeffery
IMPINJ, Inc.
LandOfFree
RFID tag design with circuitry for wafer level testing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with RFID tag design with circuitry for wafer level testing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and RFID tag design with circuitry for wafer level testing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3893794