Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With electrical contact in hole in semiconductor
Reexamination Certificate
2007-06-12
2007-06-12
Thai, Luan (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With electrical contact in hole in semiconductor
C257S774000, C257SE21597, C438S629000, C438S667000, C438S672000
Reexamination Certificate
active
10746199
ABSTRACT:
A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.
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Kripesh Vaidyanathan
Nagarajan Ranganathan
Periasamy Ganesh Vetrivel
Rotaru Mihai Dragos
Yoon Seung Uk
Ackerman Stephen B.
Agency for Science Technology and Research
Pike Rosemary L. S.
Saile Ackerman LLC
Thai Luan
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