Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-29
2004-11-23
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S290000, C438S305000
Reexamination Certificate
active
06821855
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of integrated circuit fabrication, and more specifically to a fabrication process for use in creating transistor structures in a semiconductor substrate.
2. Description of the Related Art
Currently, transistors, such as metal-oxide semiconductor field-effect transistors (MOSFET) are formed over a semiconductor substrate and are used in many integrated circuit devices. The MOSFET transistor utilizes a gate electrode to control an underlying surface channel joining a source and drain region. The substrate is doped oppositely to the source and drain regions. For example, the source and drain are of the same conductivity, e.g., N-type conductivity, whereas the channel has the conductivity of the semiconductor substrate, e.g., P-type conductivity. Typically, the gate electrode is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The channel, source, and drain are located within the semiconductor substrate.
In a typical process forming the gate electrode of a MOSFET transistor, successive blanket depositions of various layers occur. First, an insulating layer for use as a gate oxide is formed on the surface of a semiconductor substrate. Second, a conductive layer such as polysilicon is formed on top of the insulating layer. Third, a thin refractory metal layer is often deposited, such as tungsten, on top of the conductive layer which is used to form a silicide with the underlying polysilicon. An insulating layer may also be applied over the tungsten layer. This stack of layers is etched to define what ultimately becomes the gate stack for the transistor.
However, the presence of a refractory metal layer such as tungsten, can create problems during a gate stack etching process. Tungsten is a grainy and coarse metal. Accordingly, the etch front as it passes through the tungsten layer, becomes grainy and uneven resulting in a non-uniform etch which can cause undesired effects. For instance, the uneven etch front can result in undesired overetching into portions of the substrate surface. In addition, tungsten particles in the etch mixture can coat the sidewalls of the gate stack producing undesired shorts. The non-uniform etch front can also result in the polysilicon and oxide layers in the gate stack to be undesirably partially etched. If for example, the polysilicon layer is partially etched, it no longer properly functions as an effective self-aligned implant mask during source and drain implantation.
BRIEF SUMMARY OF THE INVENTION
The present invention addresses the noted problems and provides a method for forming MOSFET transistors, in which a refractory metal, such as tungsten, is not present during the gate stack etching process, but is subsequently added after gate stack etching occurs.
In the present invention, a transistor having a gate stack is produced by layering a gate oxide layer, a conducting layer, and a first insulating layer, over a semiconductor wafer; etching the respective layers to define a gate stack, implanting source and drain regions on opposite sides of the gate stack, providing an additional insulating layer over the implanted substrate and gate stack structure, forming an opening in the additional insulating layer over and down to the conducting layer, and then forming an unetched metal-containing layer, which is used to form a silicide layer over the conducting layer. In this way, a conductive layer which is used to form a silicide layer is not present during etching of the gate stack.
These and other advantages and features of the present invention will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings.
REFERENCES:
patent: 5429956 (1995-07-01), Shell et al.
patent: 5512770 (1996-04-01), Hong
patent: 5605855 (1997-02-01), Chang et al.
patent: 5686331 (1997-11-01), Song
patent: 5712501 (1998-01-01), Davies et al.
patent: 5731239 (1998-03-01), Wong et al.
patent: 5770507 (1998-06-01), Chen et al.
patent: 5891784 (1999-04-01), Cheung et al.
patent: 5981346 (1999-11-01), Hopper
patent: 6013569 (2000-01-01), Lur et al.
patent: 6043545 (2000-03-01), Tseng et al.
patent: 6251778 (2001-06-01), Fang et al.
patent: 6287925 (2001-09-01), Yu
patent: 6300201 (2001-10-01), Shao et al.
patent: 6383876 (2002-05-01), Son et al.
patent: 6423634 (2002-07-01), Wieczorek et al.
patent: 6544853 (2003-04-01), Lin
patent: 6635536 (2003-10-01), Shin et al.
patent: 0327152 (1989-08-01), None
Wolf S. “Silicon Processing for the VLSI-ERA: Vol. 2-Process Integration”, 1990, Lattice Pr., vol. 2, p. 199.
Juengling Werner
Lane Richard H.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Fourson George
Micro)n Technology, Inc.
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