Reverse lithographic process for semiconductor spaces

Details Reverse lithographic process for semiconductor spaces Reverse lithographic process for semiconductor spaces

1999-06-09

2001-08-21

Kelly, C. H. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S314000, C430S329000

Reexamination Certificate

active

06277544

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
The present application contains subject matter related to a concurrently filed U.S. Patent Application by Bhanwar Singh, Bharath Rangarajan, and Ursula Q. Quinto entitled “REVERSE LITHOGRAPHIC PROCESS FOR SEMICONDUCTOR VIAS”, Ser. No. 09/329,154, filed Jun. 6, 1999, now U.S. Pat. 6,221,777. The related application is assigned to Advanced Micro Devices, Inc.
TECHNICAL FIELD
The present invention relates generally to manufacturing of sub-micron semiconductors and more specifically to providing more densely packed semiconductor devices.
BACKGROUND ART
An integrated circuit includes a large number of closely spaced semiconductor devices formed into and on a semiconductor substrate, typically comprising silicon. Isolation structures such as field dielectrics or shallow trench dielectrics are used to electrically isolate each individual device. A major goal in the semiconductor industry has been to reduce device size and spacing to achieve denser and denser packing.
The main limitation of minimum feature size, i.e., lines and spaces, in a semiconductor process is the resolution of the optical lithography printing system. In an optical lithography printing system, radiation is directed from an illumination source through a patterned mask and onto a photoresist to reproduce the mask pattern in the photoresist. Resolution in optical lithography systems is limited by diffraction effects, which spread radiation from the illumination source into regions of the photoresist which are not directly exposed to the illumination source. Because of these diffraction effects, while it is possible to closely control the width of lines, it is very difficult, if not impossible, to control the spacing between lines.
The resolution of a lens depends on the wavelength of the illumination source and the numerical aperture of the lens. Rayleigh's criteria define two images as being resolvable when the intensity between them drops to 50% of the image intensity. These criteria are the 2d=0.61 lambda/NA, where 2d is the separation distance of two images, lambda is the wavelength of the energy source, and NA is the numerical aperture of the lens.
Commercially available optical photolithography machines are almost universally equipped with mercury vapor lamps as the illumination source. The characteristic energy spectrum of a mercury vapor lamp contains several distinct peaks at 365 nm, 248 nm, and 193 nm wavelengths. These peaks are commonly referred to by their industry designations. The peak associated with a wavelength of about 365 nm peak is the “I-line” and peaks at about 248 nm and 193 nm are deep ultra-violet or “DUV”.
Photolithography aligners are similarly designated such that it is common to speak of “I-line aligners” and “DUV aligners”. The DUV aligners utilizing energy having wavelengths of 248 nm and 193 nm to achieve better resolution than is achievable with I-line aligners.
As process technologies approach and surpass the resolvable limits of optical aligners, semiconductor manufacturers are forced to implement alternative photolithography techniques to achieve adequate resolution of the minimum features. Unfortunately, the conventional alternatives involve abandoning or substantially modifying the existing photolithography equipment at a prohibitive cost. Many wafer fabrication facilities, for example, have extensive capital investment in I-line aligners. To adequately resolve features in the sub-micron range, it is typically necessary to upgrade these aligners. Similarly, fabrication facilities with extensive investment in I-line aligners will eventually need to upgrade to DUV aligners or abandon the optical alignment equipment entirely and replace it with advanced lithography equipment including e-beam or x-ray lithography.
The cost associated with replacing or upgrading I-line and DUV photolithography equipment can be staggering. In addition to the capital required to purchase and install the improved equipment, there are extensive costs associated with qualifying the new equipment for production worthiness and training production and maintenance personnel in the operation and care of the new equipment. Similarly, in fabrication facilities that have extensive investments in I-line and DUV aligners, the costs of abandoning these aligners to achieve more densely packed devices is tremendous.
Thus, there have been intensive efforts to discover ways of using existing equipment and processes to achieve even incremental improvements in reducing spaces between and within semiconductor devices.
DISCLOSURE OF THE INVENTION
The present invention provides a reverse lithographic process for more densely packing semiconductor devices onto a semiconductor wafer. A photoresist is deposited on a semiconductor wafer which has a number of layers of semiconductor materials deposited thereon. The photoresist is patterned in a reverse photolithographic pattern with the spaces as lines. The photoresist is developed. If it is desired to make smaller spaces, the photoresist is accurately sized by plasma trimming. A polymer is deposited over the space photoresist structures. The polymer, when hardened, is subject to chemical-mechanical polishing to planarize the polymer and expose the space photoresist structures. The photoresist is then developed leaving the polymer in a reverse image of the spaces. The polymer is then used as a mask to etch the spaces. After the spaces are formed, the polymer is removed.
The present invention provides for more densely packed semiconductor devices on a semiconductor wafer by mask bias, optical proximity correction, registering process, or having smaller spaces between the semiconductor devices. The process of making fine lines by overexposure of the photoresist during the stepper-patterning sequence is used in a reverse lithographic process to form small spaces between semiconductor devices. Small spaces are difficult to pattern at underexposure conditions because scumming and bridging occurs.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.


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