Optics: measuring and testing – Inspection of flaws or impurities
Reexamination Certificate
1998-09-17
2002-10-15
Font, Frank G. (Department: 2877)
Optics: measuring and testing
Inspection of flaws or impurities
C356S237300, C356S237400, C356S394000
Reexamination Certificate
active
06466314
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to visual inspection of reticles.
BACKGROUND OF THE INVENTION
Electronic wafers are usually manufactured using a layer-by-layer methodology, with each layer's manufacture including various etching and deposition processes, which are applied with the aid of a reticle and/or a mask. To create a complete layout on a wafer, the reticle is stepped sequentially over the wafer and at each step, the pattern of the reticle is transferred to the wafer.
The reticle itself is the end product of a complicated design process in which the entire layout of the wafer is determined and tolerances are set for the manufacture process. Nevertheless, it is often the case that the final manufactured wafer deviates from the design of the reticle. The reasons for the wafer being different from the design of the reticle may include defects in the reticle manufacture and unexpected interactions between the reticle design and the process used for the wafer manufacture. Therefore, reticles are typically inspected both by the mask shop manufacturing the reticle and at the semiconductor fabrication plant (Fab). According to current practice, reticles having non-repairable defects thereon are not shipped by the mask shop or are returned by the Fab, and never used. Due to the rapid reduction in design rules (the smallest resolvable feature size), manufacturing reticles is expected to become more difficult and the price of reticles is expected to rise. Therefore, it will become more desirable to use a reticle even if it has defects in its manufacture, providing however, that such defects do not invalidate the manufactured wafer.
One method of determining which defects cause problems in wafer manufacture is to simulate the physical processes which are involved in wafer manufacture. When a reticle is inspected after its manufacture, any detected defects are analyzed based on these simulations to determine if they will have an adverse effect on the wafer manufacture. If the adverse effect is within certain tolerances, the reticle is accepted. These simulations may also be used to generate a set of rules that govern which defects in a reticle are acceptable and which are not.
A critical problem with this approach is that the physical process must be understood in order to be simulated. Specifically, a simulation model of the stepper and fabrication process are first constructed. These models require expertise and knowledge of each stepper-fabrication combination, including, for example, the type of stepper used, the technology used to print the wafer and the development process. A new model may be required for each new combination of stepper, exposure and other processing steps and/or parameters. In some cases, a physical understanding of the parameters of the process are not available. As a result, Fab technicians are often uncomfortable relying on a model instead of on the actual equipment used in the Fab.
SUMMARY OF THE INVENTION
One object of some embodiments of the invention is to provide a method of reticle inspection which takes into account physical processes involved in printing a wafer based on the reticle. Preferably however, a detailed knowledge or analysis of the physical processes is not required.
One aspect of some preferred embodiments of the present invention relates to the generation of a test reticle comprising a plurality of pattern-features, generating a wafer using the reticle and determining which defects in the reticle result in unacceptable defects in the wafer and which do not. Throughout this specification, the term “pattern-features” is a short hand to signify either or both of “design features” and “test defects.” Design features relate to features that correlate to the design of the circuitry to be printed. Test defects relates to defects which are intentionally introduced onto the test reticle. Both design features and test defects can be inspected for transferability. For example, design features can be inspected for the quality of their transfer, and test defects can be inspected to check whether they “print” onto the wafer.
In a preferred embodiment of the invention, any defects which transfer from a reticle to the wafer are considered unacceptable. Defects in a reticle which do not transfer to a wafer may be considered acceptable. The determination may be absolute or it may include certain tolerances. Alternatively or additionally, even if the defect have an effect on the wafer layout, such defects are graded responsive to whether or not they affect the functionality of the wafer. Alternatively or additionally to using a test-reticle, the transfer of defects may be manually or automatically identified on existing reticles.
Another aspect of some preferred embodiments of the invention relates to training a neural network with the results of the determination of defect transfer. Preferably, the neural network is then used as part of a reticle inspection process, whereby detected defects on the reticle are analyzed using the neural network to determine if they transfer, as defects, to the manufactured wafer.
Another aspect of some preferred embodiments of the invention is that the entire process of the reticle testing can be done without any in-depth knowledge of the printing, development and/or fabrication processes involved.
A neural network training method, in accordance with a preferred embodiment of the invention comprises designing and manufacturing a test reticle, printing the circuit onto a wafer and checking the generated wafer for defects. The defects in the wafer are then matched to defects in the reticle using the known coordinates of the designed test defects. Additionally, the reticle can be inspected for additional unintended defects and their coordinates can be stored in the system's memory. The wafer is then analyzed to see if the defects transferred as unacceptable defects onto the wafer. In some cases, unacceptability is simply that the defect transferred to the wafer, in other cases, unacceptability may be dependent on the functional effect of the transferred defect. In some cases, a defect for one use, may not be a defect for another, less demanding use. In a preferred embodiment of the invention, the neural network is trained by associating particular defects in the reticle with the acceptability of the resulting wafer.
Preferably, the test reticle used is a specially designed test reticle which contains a variety of predetermined pattern-features, some of which may be defective pattern-features. Additionally, the test reticle preferably includes especially designed defects. Alternatively, reticle-wafer sets that are known to contain defects may be used for training. Preferably, the defects are repeated for various dimensions and/or tolerances of the defect. Alternatively or additionally, the defects are repeated on the reticle so that a statistical evaluation of the defect transfer probability can be obtained. Alternatively or additionally, one or more wafers are generated using a plurality of different reticles and/or a plurality of different focus-exposure settings and/or a plurality of different process parameters, so that such statistics may be determined.
As noted above, in a preferred embodiment of the invention, the test reticle includes both a defected and a defect free example of each of a plurality of pattern features and a plurality of designed defects. Then, when analyzing the exposed wafer, the transfer of the defective patterns may be compared to the transfer of the non-defective patterns. Additionally, the wafer can be inspected according to the coordinates of the designed defects to determine whether they had transferred onto the wafer.
In a preferred embodiment of the invention, a combinatorial set of defect cells is produced, including, feature type, defect type and/or defect features. For example, a defect type “non constant width” may be matched with a feature “1 micron conductor” and a defect feature “variation>10%”. Each such cell preferably includes a defected feature-pat
Applied Materials Inc.
Sughrue Mion Zinn Macpeak and Seas LLP
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