Response bits as stimulus in subdivided scan path delay test

Details Response bits as stimulus in subdivided scan path delay test Response bits as stimulus in subdivided scan path delay test

2005-04-11

2008-10-14

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07437639

ABSTRACT:
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present invention improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.

REFERENCES:
patent: 5347523 (1994-09-01), Khatri et al.
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patent: 5606568 (1997-02-01), Sudweeks
patent: 5717702 (1998-02-01), Stokes et al.
patent: 6401226 (2002-06-01), Maeno
patent: 6516432 (2003-02-01), Motika et al.

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