Resolution of hemispherical grained silicon peeling and row-dist

Details Resolution of hemispherical grained silicon peeling and row-dist Resolution of hemispherical grained silicon peeling and row-dist

1998-06-11

1999-03-02

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, 438255, 438397, 438398, H01L 218234, H01L 218242, H01L 2120

Patent

active

058770526

ABSTRACT:
A method for creating stacked capacitor structures, with increased surface area, obtained using storage node electrode structures comprised of an HSG silicon layer, on a heavily doped amorphous silicon layer, both overlying polysilicon storage node shapes, has been developed. A dilute hydrofluoric acid pre-clean procedure is used prior to depositing a heavily doped amorphous silicon layer, on underlying polysilicon storage node shapes. An overlying second amorphous silicon layer is in situ deposited, in the same furnace used for the prior deposition of heavily doped amorphous silicon layer, followed by an in situ seeding/annealing procedure, converting the second amorphous silicon layer to an HSG silicon layer. This invention features the use of the acid pre-clean, to improve adhesion of the heavily doped amorphous silicon layer, to underlying polysilicon storage node shapes. In addition the width of the polysilicon storage node shapes is initially designed to be narrow, to accept subsequent amorphous silicon depositions, and thus to result in the desired spacing between storage node electrodes, after deposition of the amorphous silicon layers, on the sides of the polysilicon storage node shapes.

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patent: 5763306 (1998-06-01), Tsai

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