Resizable and relocatable memory scratch pad as a cache slice

Details Resizable and relocatable memory scratch pad as a cache slice Resizable and relocatable memory scratch pad as a cache slice

1996-10-18

1999-10-12

Asta, Frank J.

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

711128, 711129, 711169, 711170, 711171, 711172, G06F 1200

Patent

active

059667346

ABSTRACT:
A cache system supports a re-sizable software-managed fast scratch pad that is implemented as a cache-slice. A processor register indicates the size and base address of the scratch pad. Instructions which facilitate use of the scratch pad include a prefetch instruction which loads multiple lines of data from external memory into the scratch pad and a writeback instruction which writes multiple lines of data from the scratch pad to external memory. The prefetch and writeback instructions are non-blocking instructions to allow instructions following in the program order to be executed while a prefetch or writeback operation is pending.

REFERENCES:
patent: 5067078 (1991-11-01), Talgam et al.
patent: 5517626 (1996-05-01), Archer et al.
patent: 5619676 (1997-04-01), Fukada et al.
patent: 5619680 (1997-04-01), Berkovich et al.
patent: 5721874 (1998-02-01), Carnevale et al.
patent: 5737750 (1998-04-01), Kumar et al.
Jim Handy, The Cache Memory Book, 1993.

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