Resistive cell structure for reducing soft error rate

Details Resistive cell structure for reducing soft error rate Resistive cell structure for reducing soft error rate

2007-01-29

2009-02-03

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S063000, C365S148000, C365S156000, C257S368000, C257S369000

Reexamination Certificate

active

07486541

ABSTRACT:
A memory cell for reducing soft error rate and the method for forming same are disclosed. The memory cell comprises a first bit line signal (BL), a second bit line signal complementary to the first bit line signal (BLB), a first pass gate coupled to the BL, a second pass gate coupled to the BLB, a first inverter whose output node receives the BL through the first pass gate, a second inverter whose output node receives the BLB through the second pass gate, a first instrument coupled between the output node of the first inverter and an input node of the second inverter, and a second instrument coupled between the output node of the second inverter and an input node of the first inverter, wherein the first and second instruments increase voltage discharge time of the memory cell when voltages at the output nodes of the inverters accidentally discharge.

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