Resistance defect assessment device, resistance defect...

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

Reexamination Certificate

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C257SE21521, C257SE21524

Reexamination Certificate

active

10895833

ABSTRACT:
A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device including test patterns capable of measuring a resistance variation component to be the resistance variation defect in each chip area or each shot area of the wafer, wherein the number of test patterns included in one chip area or one shot area is set so that it is possible to estimate the yield of the integrated circuit device.

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Charles Weber, “Standard Defect Monitor”, 1988 IEEE Proceedings on Microelectronic Test Structures, vol. 1, No. 1, Feb. 1988, pp. 114-119.
Andrew Grenville, et al., “Electrical Critical Dimension Metrology for 100-nm Linewidths and Below”, in Optical Microlithography XIII, Proceedings of SPIE, vol. 4000, 2000, pp. 452-459.
Takeshi Hamamoto, et al., “Measurement of Contact Resistance Distribution Using a 4k-Contacts Array”, IEEE Transactions on Semiconductor Manufacturing, vol. 9, No. 1, Feb. 1996, pp. 9-14.

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