Resist pattern forming method

Details Resist pattern forming method Resist pattern forming method

2000-09-07

2003-10-14

Huff, Mark F. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Forming nonplanar surface

C430S311000, C430S394000, C430S396000, C430S005000, C430S022000

Reexamination Certificate

active

06632592

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-256205, filed Sep. 9, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a lithography technology for semiconductors, and, more particularly, to a resist pattern forming method for forming a gate pattern or the like on a resist film on a wafer.
The integration level of LSIs is ever improving and the design rules for interconnection or the like inside LSIs are becoming smaller and smaller. With the reduction in design rules, the photolithography technology is advancing. For example, the exposure wavelength is shortened from the wavelength of a KrF excimer laser (wavelength of 248 nm) to the wavelength of an ArF excimer laser (wavelength of 193 nm) and the diameter of the light emitting lens of an exposure apparatus is made larger (larger numerical aperture), thus leading to an improvement on the resolution.
It is known from the Rayleigh's equation that the resolution R is given by the following equation:
R=k
1
(&lgr;/
NA
)  (1)
where &lgr; is the exposure wavelength, NA is the numerical aperture and k
1
is a constant which is determined by a process of a resist or the like. It is understood from the equation 1 that &lgr; should be made smaller or NA should be made larger in order to improbe the resolution.
In the actual mass production, the yield falls unless a certain degree of or higher process margin is secured. One important index for the process margin is a focus depth (DOF) which is expressed by
DOF=k
2
(&lgr;/NA
2
)  (2)
where k
2
is a constant. It is apparent from the equation 2 that &lgr; should be made greater or NA should be made smaller in order to increase DOF.
It is apparent from the equations 1 and 2 that increasing the resolution by increasing NA reduces DOF. As DOF decreases by a factor of the square of NA, increasing NA drastically reduces DOF. To ensure both certain levels of resolution and process margin, therefore, it is desirable that NA and &lgr; should both be small.
With regard to the gate patterns of transistors, the uniform operational performance of transistors is demanded, so that the gate line width should be controlled strictly. This requires that lithography for forming a gate pattern have a sufficient process margin. In forming minute gate patterns, therefore, NA cannot be made so large while the exposure wavelength &lgr; may be made shorter.
In forming the gate of a transistor, the gate pattern is formed on a resist by performing single exposure on the gate portion and the other, contact pad and minute space portions using the same mask. One consideration that should be taken in this case is the fact that the gate pattern as well as a contact pattern and other patterns lie on the layer where the gate is to be formed. When minute space is present on such a layer, in particularly, the minute space cannot be formed with a high resolution if NA is small. This means that reducing NA has a limit.
For a repeated pattern portion in a dynamic RAM or the like where cells are densely located, a high resolution is demanded so that a larger NA is desirable. By contrast, the peripheral portion of a cell has a large pattern size and does not have fewer dense patterns, requiring the focus depth more than the resolution. It is therefore desirable to have a smaller NA. In the case of exposing the cell portion and the peripheral portion with the same mask, therefore, the optimal NA may not exist.
Because there are many isolated lines in the gate portion where line width control is required in the formation of the gate pattern of a transistor in minute patterns which demands a dimensional precision, the numerical aperture NA of an exposure apparatus should be small from the viewpoint of the process margin. However, exposure with a small numerical aperture NA ay disable the formation of some of other patterns than the gate portion which do not require line width control. This problem could not be overcome even by changing the conditions of the exposure apparatus.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a resist pattern forming method which has a sufficient process margin for a gate pattern and a sufficient resolution for a minute pattern of space or the like.
It is another object of this invention to provide an exposure apparatus that ensures a sufficient process margin for an isolated pattern whose peripheral portion has a large size while keeping a certain level of resolution for a repeated pattern in a dynamic RAM or the like which is densed with cells
To achieve the above objects, according to one aspect of this invention, there is provided a resist pattern forming method of forming a resist pattern by exposing continual gate patterns inside and outside an active area onto a resist film formed on a wafer having the active area pattern on a major surface using a projection exposure apparatus, comprising the steps of exposing those gate patterns that lie in the active area onto the resist film under a condition that an numerical aperture of the projection exposure apparatus is small; and exposing those gate patterns that lie outside the active area onto the resist film under a condition that the numerical aperture of the projection exposure apparatus is large.
According to another aspect of this invention, there is provided a resist pattern forming method of forming a resist pattern by exposing a pattern of a memory cell portion and a pattern of an other portion than the memory cell portion on a resist film formed on a wafer using a projection exposure apparatus, comprising the steps of exposing the pattern of the memory cell portion onto the resist film under a condition that an numerical aperture of the projection exposure apparatus is large; and exposing the pattern of the other portion than the memory cell portion onto the resist film under a condition that the numerical aperture of the projection exposure apparatus is small.
According to a further aspect of this invention, there is provided a resist pattern forming method of forming a resist pattern by exposing continual gate patterns inside and outside an active area onto a resist film formed on a wafer having the active area pattern on a major surface using a projection exposure apparatus, comprising a first step of resizing a pattern equivalent to an active area on the wafer; a second step of inverting the pattern resized in the first step; a third step of obtaining a logical product of the pattern resized in the first step and a gate pattern to be exposed; a fourth step of forming a first mask having a pattern equivalent to a logical sum of the inverted pattern formed in the second step and the logical product pattern formed in the third step; a fifth step of forming a second mask having a pattern equivalent to a logical sum of the pattern resized in the first step and the gate pattern to be exposed; a sixth step of exposing the resist film on the wafer using the first mask formed in the fourth step under a condition that an numerical aperture of the projection exposure apparatus is small; and a seventh step of exposing the resist film on the wafer using the second mask formed in the fifth step under a condition that the numerical aperture of the projection exposure apparatus is large.
According to a still further aspect of this invention, there is provided a resist pattern forming method of forming a resist pattern by exposing continual gate patterns inside and outside an active area onto a resist film formed on a wafer having the active area pattern on a major surface using a projection exposure apparatus, comprising the steps of resizing a pattern equivalent to an active area on the wafer; inverting the resized pattern; obtaining a logical product of the resized pattern and a gate pattern to be exposed; forming a first mask using the inverted pattern as a light shielding

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