Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated
Reexamination Certificate
1999-03-02
2001-02-20
Picardàt, Kevin M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
C257S773000, C257S778000, C257S780000
Reexamination Certificate
active
06191493
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a resin seal semiconductor package accommodating a semiconductor component and a manufacturing method of the same. In particular, the invention relates to the resin seal semiconductor package which can achieve a high performance and a high reliability as well as reduction in size, and also relates to the manufacturing method of the same.
2. Description of the Related Art
Semiconductor packages are well-known containers for accommodating semiconductor components. Two kinds of materials, i.e., ceramics and resin, are generally known as the material of the semiconductor packages. Of these materials, the semiconductor packages made of resin have been broadly used as commercial packages because of low material costs and high mass-productivity. A conventional example of the package made of resin, i.e., a so called resin seal semiconductor package will be described below.
FIG. 95
is a perspective view partially in section showing an example of the conventional resin seal semiconductor package. Referring to
FIG. 95
, a semiconductor chip
103
on which elements are formed is disposed on a die pad
107
made of Fe—Ni alloy or the like. Bonding pads
104
which function as external I/O electrodes are formed on a main surface of the semiconductor chip
103
. Around the die pad
107
, there are disposed internal leads
105
and external leads
102
for electrical connection with electrodes of external equipments.
The bonding pads
104
and the internal leads
105
are electrically connected together by bonding wires
106
made of gold (Au) or the like. Thereby, elements formed on the semiconductor chip
103
and the external equipments are electrically connected. The die pad
107
, semiconductor chip
103
and internal leads
105
are covered with seal resin
101
.
The above resin seal semiconductor package suffers from following problems because of the structure described above. The conventional structure requires the bonding wires
106
, internal leads
105
and external leads
102
for electrically connecting the elements and external equipments. Regions in which the bonding wires
106
and internal leads
105
are formed cause a problem.
Since the regions for the bonding wires
106
and internal leads
105
are required around the semiconductor chip
103
, the seal resin
101
has a width larger by about 1 mm than a width of the semiconductor chip
103
. This impedes reduction of the package size.
Further, connections (i.e., bonding wires
106
, internal leads
105
and external leads
102
) for the external equipments are relatively long, which deteriorates electrical performance because of an increase of the impedance component.
Three improvements aimed at reduction of the package sizes and improvement of the electrical performance have been proposed for overcoming the above problems. These improvements will be described below with reference to
FIGS. 96-99
.
FIG. 96
is a cross section showing a resin seal semiconductor package of a first improvement disclosed in Japanese Patent Laying-Open No. 3-104141 (1991). Referring to
FIG. 96
, bonding pads
114
are formed on a main surface of a semiconductor chip
113
. Protruded electrodes
112
to be electrically connected to external equipments are formed on the bonding pads
114
. The protruded electrodes
112
may be made of solder (Pb/Sn) or other electrically conductive material plated with solder. Tip ends of the protruded electrodes
112
are protruded externally through a seal resin
111
covering the semiconductor chip
113
.
Owing to the structures described above, the resin seal semiconductor package of the first improvement comes to have a size nearly equal to that of the semiconductor chip
113
, and thus can be smaller than conventional semiconductor packages. Further, the connections (i.e., protruded electrodes
12
) for external equipments can be made shorter than the conventional connections, so that the electrical property can be improved.
A second improvement will now be described below with reference to
FIGS. 97 and 98
.
FIG. 97
is fragmentary cross section showing a resin seal semiconductor package of the second improvement disclosed in Japanese Patent Laying-Open No. 4-207046 (1992). In
FIGS. 98A
to D are perspective views partially in section showing different steps in a process of manufacturing the resin seal semiconductor package in FIG.
97
.
Referring first to
FIG. 97
, a bonding pad
124
is formed on a main surface of a semiconductor chip
123
. A protection film
126
is formed on the main surface of the semiconductor chip
123
. The protection film
126
has an opening which is located on a portion of a surface of the bonding pad
124
. The protection film
126
and the semiconductor chip
123
form a semiconductor element
125
.
A seal resin
121
is formed over the protection film
126
. The seal resin
121
is provided with an opening
121
a
located above the bonding bad
124
. A protruded electrode
122
protruded from the surface of the seal resin
121
is formed in the opening
121
a
and is located on the bonding pad
124
. Metal of a low melting point or electrically conductive resin is disclosed as the material of protruded electrode
122
.
A method of manufacturing the resin seal semiconductor package of the second improvement thus structured will be described below with reference to
FIGS. 98A-98D
. Referring first to
FIG. 98A
, a plurality of bonding pads
124
are formed at predetermined positions on the main surface of the semiconductor chip
123
. The protection film (not shown in
FIGS. 98A-98D
) is formed such that the openings thereof are located on portions of the surfaces of the bonding pads
124
. In this manner, the semiconductor element
125
is formed.
In
FIG. 98B
, the seal resin
121
is formed on the main surface of the semiconductor element
125
. Then, as shown in
FIG. 98C
, the openings
121
a
extending to the bonding pads
124
are formed at portions of the seal resin
121
located above the bonding pads
124
. As shown in
FIG. 98D
, the openings
121
a
are filled with conductive material to form the protruded electrodes
122
.
Owing to the structures described above, the second improvement can reduce the size of the package and improve the electrical performance similarly to the first improvement.
A third improvement will be described below with reference to
FIG. 99
, which is a cross section of a resin seal semiconductor package disclosed in Japanese Patent Laying-Open No. 4-139848 (1992). In
FIG. 99
, an interconnection layer
135
and bonding pads
134
are formed on a surface of a semiconductor chip
133
.
The interconnection layer
135
is covered with a protection film
136
having openings located on portions of surfaces of the bonding pads
134
. Bonding pads
134
are connected to columnar electrodes
132
formed thereon. The semiconductor chip
133
is sealed with a seal resin
131
which exposes only top surfaces of the electrodes
132
.
Owing to the above structures, the third improvement can reduce the size of the semiconductor package and improve the electrical performance similarly to the first and second improvements.
As described above, the resin seal semiconductor packages of the first to third improvements have such advantages that the size of the semiconductor packages can be reduced and the electrical performance can be improved, but they respectively have following problems, which will be described below with reference to
FIGS. 100-103
.
First, the problem of the first improvement will be described below with reference to
FIGS. 100 and 101
.
FIG. 100
is a cross section schematically showing a problem of the protruded electrode
112
made only of solder.
FIGS. 101A and 101B
are cross sections showing different steps for connecting the semiconductor package to the interconnection on a printed board in the case where a solder
115
is plated on the top surface of the protruded electrode
112
.
Referring to
FIG. 100
, if the protruded electrode
11
Baba Shinji
Matsuo Mitsuyasu
Matsushima Hironori
Nakao Shin
Yasunaga Masatoshi
Collins D. M.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Picardat Kevin M.
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