Resin overmolded type semiconductor device

Details Resin overmolded type semiconductor device Resin overmolded type semiconductor device

1999-12-13

2001-07-24

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257S738000, C257S777000, C257S778000, C257S780000

Reexamination Certificate

active

06265783

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
This application is related to Japanese patent application No. HEI 11(1999)-018225 filed on Jan. 27, 1999 whose priority is claimed under 35 USC §119, the disclosure of which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a resin overmolded type semiconductor device and, more particularly, to a resin overmolded type semiconductor device having a reduced size close to a chip size.
2. Description of the Prior Art
In recent years, resin overmolded type semiconductor devices have widely been used which include chip size packages (CSPs) such as QFPs (quad flat packages) and BGA (ball grid array) packages which meet demands for reduction of the size (thickness and plan surface area) and weight of electronic systems and for automation of fabrication processes. Since a semiconductor chip contained in such a semiconductor device is required to meet demands for higher-speed signal processing and higher performance, it is necessary to provide a greater number of external connection terminals on the semiconductor device.
In such a case, the semiconductor device employs a BGA package which has external connection terminals two-dimensionally arranged in a matrix array on a bottom face thereof. Further,the size of the semiconductor device is reduced as much as possible or close to a chip size for incorporation of the semiconductor device in a small size portable system. One exemplary BGA package is constructed such that a semiconductor chip formed with a MOS transistor and the like is mounted face-up on an interconnection board by a wire bonding method for connection to external connection terminals via interconnection patterns.
As shown in
FIG. 9
, a resin overmolded semiconductor device of the prior art comprises: an interconnection board including an insulative substrate
5
formed with interconnection patterns
6
having wire connection portions, lands
10
and interconnections connecting the wire connection portions to the lands
10
, and an interconnection protective film
7
of a solder resist; a semiconductor chip
1
bonded on the interconnection board by an adhesive film
8
; wires
3
connecting electrode pads of the semiconductor chip
1
to the interconnection patterns
6
; a resin sealer
2
sealing one side of the interconnection board for protection of the semiconductor chip
1
and the wires
3
; and external connection terminals
4
formed on a lower face of the insulative substrate
5
as solder balls which extend through through-holes formed in the insulative substrate
5
for connection to the lands
10
of the interconnection patterns
6
. The resin overmolded semiconductor device is mounted along with resistors and capacitors on a mount board, which is in turn incorporated in a small size portable system.
The external connection terminals
4
of the resin overmolded semiconductor device having a size close to a chip size are uniformly arranged over the lower face of the semiconductor device or, if the number of the external connection terminals
4
is small, arranged in a peripheral portion, but not entirely nor in a central portion, of the lower face of the semiconductor device as shown in
FIGS. 9 and 10
. This is because arranging the external connection terminals in the peripheral portion is more advantageous for the interconnection on the mount board than arranging the external connection terminals at a greater pitch over the entire lower face.
In some cases, conversely, the external connection terminals are arranged only in the central portion of the resin overmolded semiconductor device as shown in FIG.
11
. This arrangement is employed to allow semiconductor devices such as memory devices having different capacities and different package sizes (chip sizes) to have a common signal terminal array.
In some cases, land patterns are formed in a portion of an upper face (chip-side face) of the insulative substrate of the semiconductor device where neither the external connection terminals nor the through-holes are formed therebelow as shown in
FIGS. 10 and 11
. With this arrangement, the upper face of the interconnection board on which the chip is mounted is planarized, so that formation of a void under the chip can be prevented which may otherwise occur due to presence of an air bubble during a chip mounting process. Thus, the semiconductor device is prevented from suffering from thermal defect during a reflow process. Provision of no dummy solder ball in the central portion of the lower face of the semiconductor device suppresses an increase in the cost of a solder ball material, a reduction in the productivity, and a reduction in the planarity of the external connection terminals, and increases routing flexibility of interconnection on the mount board.
The aforesaid resin overmolded semiconductor device, which is of a small size and has an area array structure, is mounted on the mount board through the reflow process. Since the interconnection patterns are present under the solder resist film on the interconnection board, the surface of the solder resist film is not planar. If the planarity of the solder resist film on the interconnection patterns is reduced, a die-bonding pressure cannot sufficiently be applied onto a depressed portion of the solder resist film when the semiconductor chip is die-bonded onto the solder resist filmwith the use of the adhesive film, thereby failing to provide a sufficient adhesion strength between the adhesive film and the solder resist film.
In s uch a case, moisture Is liable to be adsorbed on a n interface between the solde r resist film and the adhesive film. Since the Interconnection board, the solder resist f ilm and the adhesive f ilm are each composed of an organic material, not only the bonding interf ace but also these components have moisture adsorptive properties. When the semiconductor device is subjected to rapid heating In the reflow process, the moisture contained in the semiconductor device is rapidly heated to be expanded. Hence, the semiconductor device suffer from apparent defects such as separation of the interconnection board from the resin sealer and breakage of the interconnection patterns.
For prevention of the separation of the bonded surfaces and a like inconvenience which may occur when the resin overmolded semiconductor device is mounted on the mount board through the reflow process, Japanese Unexamined Patent Publication No. 9-12100 2(1997) proposes a resin overmolded semiconductor device which is constructed such that small holes
13
are formed in an insulative substrate thereof to effectively release moisture from the inside thereof as shown in FIG.
12
.
In general, the interconnection board of the resin overmolded semiconductor device is produced by forming through-holes in a polyimide insulative substrate on which an adhesive is applied, bonding a Cu foil on the substrate, patterning the Cu foil to form interconnection patterns, applying a solder resist on the interconnection patterns by printing, and performing Au plating. If the formation of the small holes are carried out simultaneously with the formation of the through-holes, the solder resist undesirably spreads to the lower side of the substrate on which the solder balls are to be provided during the printing of the solder resist.
For prevention of the spreading of the solder resist, the formation of the small holes may be carried out after the printing of the solder resist, but additionally requires a punching die and a hole formation step. Therefore, the formation of the small holes is not desirable. Without the provision of the small holes for the release of the moisture, however, there is a possibility that the substrate may swell when the semiconductor device is rapidly heated during the mounting thereof through the reflow process.
During the reflow process, the swelling occurs mainly in a region of the insulative substrate where no external connection terminal is present. This is because water vapor

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