Rescheduling data input and output commands for bus...

Details Rescheduling data input and output commands for bus... Rescheduling data input and output commands for bus...

1999-11-17

2003-10-21

Lee, Thomas (Department: 2185)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Reexamination Certificate

active

06636978

ABSTRACT:

FIELD OF THE INVENTION
This invention is generally related to inter-chip communication, and more particularly, to a communication protocol employed for rescheduling purposes to achieve communication at any frequency.
BACKGROUND OF THE INVENTION
The evolution of sub-micron CMOS technology has steadily improved the performance of microprocessors. Quadrupling every three years, it has prompted the development of product chips having clock frequencies exceeding 500 MHz, even attaining, at least on an experimental basis, clock frequencies of the order of 1 GHz. It is highly desirable to have memories, such as Dynamic Random Access Memories (DRAM), characterized not only by their high density but also by their high performance. Synchronous DRAMs (SDRAMs) typically use a 3-stage pipelined architecture and a 2-bit pre-fetch architecture for a consecutive column burst operation provided with an internal burst address counter, improving the data rate to 125 Mb/sec per pin for prior generation 16 Mb memories. Thereafter, 64 Mb SDRAMs introduced an address incremented pipeline scheme, increasing the data rate to 150 Mb/sec per pin. Still after, 256 Mb SDRAMs resorted to a wave-pipeline scheme with first-in first-out (FIFO) circuitry, boosting the data rate to approximately 250 Mb/sec per pin. Taking a more drastic step, the 72 Mb RAM bus DRAM (RDRAM) employing an 8-bit pre-fetch and a protocol based design provided with RAM Bus-Signalling-Level (RSL) interfaces, achieve frequencies as high as 800 Mb/sec per pin×16 DQs, resulting in 1.6 Gb/sec.
As the speed of memories improves, it is particularly important to optimize the communication between the microprocessor and the memory.
FIG. 1
a
shows a conventional system (
100
) that establishes communication between a driver chip (
110
) and a receiver chip (
120
). When operating in a memory read access mode, the driver chip (
110
) is the memory and the receiver chip (
120
) is the microprocessor. When operating in a memory write access mode, the driver chip (
110
) is the microprocessor and the receiver chip (
120
) is the memory. Practitioners will fully realize that when implementing an actual system, a controller is required to establish data communication between the chip (
130
), the driver chip (
110
) and the receiver chip (
120
).
The detailed operation of the system (
100
) is explained with reference to the timing diagram shown in
FIG. 1
b.
For simplicity sake, the discussion that follows assumes a single data rate of communication synchronized to a reference clock (CLK
REF
). However, the inventive method to be described hereinafter is not limited to the configuration shown, but it also applies to a double data rate communication with or without source synchronization. The driver chip (
110
) outputs data in synchronism with CLK
REF
on the data bus (DQ) following an output latency (LAT
OUT
), which is measured from the time an output event command is recognized. More particularly, the output event is recognized when an output command signal (CMD
OUT
) is at 0 at the leading edge of a reference clock (CLK
REF
). The data is outputted to the data bus (DQ) driven by clock CLK
REF
after a lapse of a predetermined number of clock cycles. This is defined as the output latency (LAT
OUT
). The receiver chip (
120
) receives data from the data bus (DQ) after a lapse of the input latency (LAT
IN
), which is defined as the number of clock cycles after an event command is recognized. More particularly, the input event is recognized when an input command signal (CMD
IN
) is at 0 at the leading edge of CLK
REF
. Input data is received from the data bus (DQ) in synchronism with CLK
REF
following a number of clocks cycles. This number is defined as the input latency (LAT
IN
). The control chip (
130
) predetermines the output latency LAT
OUT
as well as the input latency LAT
IN
applicable to the driver chip (
110
) and the receiver chip (
120
) by following LAT
IN
and LAT
OUT
rules. The control chip (
130
) schedules the output command (CMD
OUT
) and the input command (CMD
IN
) to successfully establish communication between the driver chip (
110
) to the receiver chip (
120
). In an actual system, the control chip (
130
) is the memory controller. Scheduling data between LAT
OUT
, LAT
IN
, CMD
IN
, and CMD
OUT
follows certain rules of communication in synchronism with CLK
REF
, which are applicable to the transfer of data from the driver chip (
110
) to the receiver chip (
120
) via the data bus (DQ). By way of example, and still referring to the same timing diagram, the scheduling of CMD
OUT
and CMD
IN
is shown for LAT
OUT
=2 and LAT
IN
=1.5. Note that the output data from driver chip (
110
) is available at a time when the data input event for the receiver chip (
120
) is enabled, resulting in a successful data communication. As the chip-to-chip communication frequency increases, synchronization with the reference clock (CLK
REF
) becomes more difficult to achieve since the internal operation of the system is usually referenced by the same reference clock CLK
REF
.
FIG. 2
illustrates a first example showing a synchronization error (t
err
) applicable to the driver chip (
110
). The following example assumes an output latency LAT
OUT
of 1, although LAT
OUT
may take any value. Internal output event control signal (CTRL
OUT
) switches to 1 when the output event is recognized (i.e., when CMD
OUT
is detected at the leading edge of the CLK
REF
). The presence of detection logic delays the actual recognition by an amount of time t
1
. The output event is enabled by detecting the leading edge of CLK
INT
when CTRL
OUT
is at 1. The actual output is valid even after t
2
as a result of the presence of the output logic. The internal event recognition and the output logic delays t
1
and t
2
cause the actual output to introduce a synchronization error t
err
with respect to CLK
REF
. To avoid the problem of t
err
shown in
FIG. 2
, a DLL (Delayed Locked Loop) has often been advantageously used to create a compensated internal clock version which leads the reference clock (CLK
REF
) by a negative time delay t
2
.
Still referring to driver chip (
110
) and with reference to
FIG. 3
, an example that uses the aforementioned DLL compensation shows an output being synchronized to the reference clock (CLK
REF
). Let it be assumed that the system output is enabled by the leading clock (CLK
INT
) which compensates for the error t
2
when using DLL compensation. Because of this negative CLK
INT
compensation by t
2
of CLK
REF
, after a time delay t
2
, the output successfully synchronizes to the reference clock (CLK
REF
). This DLL compensation works well at low frequencies (<200 Mhz). However, as the clock frequency increases, a problem with the digital shift surfaces when CLK
INT
compensates for the lapse of t
2
occurring prior to the output event recognition, causing a digital latency shift condition.
FIG. 4
illustrates the problem which causes a digital latency shift. The output recognition event defined by the leading edge of the CTRL
OUT
occurs at a time subsequent to the target leading edge of CLK
INT
. Thus, the driver chip detects the next leading edge of the target leading edge of CLK
INT
. As a result, the output occurs exactly one clock cycle later than the target. This causes a digital latency shift or offset between the predetermined latency (LAT
OUT
) and the actual latency (ALAT
OUT
) Mathematically, a digital shift occurs when t
1
+t
2
>=T
REF
, where T
REF
represents the CLK
REF
cycle time, as shown. Thus, the digital shift is cycle-time dependent, the cycle-time of the first digital shift occurring when T
REF
=(t
1
+t
2
). Multiple cycles of n digital shifts occur when t
1
+t
2
>=nT
REF
, wherein n is an integer greater than or equal to 1 representing the number of digital shifts. Thus, n=1 results in a single digital shift, as described above. This problem causes multiple digital shifts for the predetermined latency (LAT
OUT
) command when an ou

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