Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1997-12-23
1999-05-04
Dinh, Son T.
Static information storage and retrieval
Read/write circuit
Bad bit
365 63, 36523001, G11C 700
Patent
active
059010959
ABSTRACT:
A reprogrammable address selector is incorporated in an embedded DRAM array which has a plurality of addressable DRAM components. The reprogrammable address selector responds to an address signal defining a unique response address. One of a plurality of selected response addresses may be electrically and selectively programmed into the selector as a substitute for a fixed response address. Thereafter the addressable DRAM component responds to the programmed response address rather than the fixed response address. The programmed response address is programmed from address signals applied on the bus.
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Bailey Wayne P.
Dinh Son T.
Ley John R.
LSI Logic Corporation
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