Repair apparatus and method for semiconductor memory device...

Details Repair apparatus and method for semiconductor memory device... Repair apparatus and method for semiconductor memory device...

2005-09-06

2005-09-06

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

06940765

ABSTRACT:
Provided are a repair apparatus and method in a semiconductor memory device, the repair apparatus being selectively programmed suitable for a wafer-level test or a post package test. The repair apparatus includes a repair control circuit, a redundancy memory cell array, and a redundancy decoder. The repair control circuit programs one of an address signal for a first defective cell of the main memory cell array and an address signal for a second defective cell of the main memory cell array and outputs a control signal in response to the address signal undergoing the first decoding operation, the first defective cell being detected during a wafer-level test and the second defective cell being detected during a post package test. The redundancy memory cell array includes a plurality of redundancy memory cells and is activated to repair one of the first and second defective cells. The redundancy decoder is enabled or disabled in response to the control signal and is enabled to activate parts of the redundancy memory cells. The normal decoder is disabled in response to the control signal when the redundancy decoder is enabled.

REFERENCES:
patent: 5576999 (1996-11-01), Kim et al.
patent: 6465261 (2002-10-01), Kang
patent: 6754094 (2004-06-01), McClure
patent: 1997-003948 (1997-01-01), None

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