Relaxed write timing for a memory device

Details Relaxed write timing for a memory device Relaxed write timing for a memory device

1998-05-13

2000-02-15

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518908, 365191233, G11C 1604

Patent

active

060260319

ABSTRACT:
A memory device provides a relaxed write timing scheme that improves access time. The address and/or the data is set up to the memory array during a previous write cycle so that the next write cycle can proceed without delays produced in delivering the address and/or the data to the array during the write cycle in which the data is to be written to the array.

REFERENCES:
patent: 5581512 (1996-12-01), Kitamura
patent: 5752270 (1998-05-01), Wada

Affiliated with

Also associated with

Rating

Relaxed write timing for a memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Relaxed write timing for a memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Relaxed write timing for a memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1911221