Register structure with a dual-ended write mechanism

Details Register structure with a dual-ended write mechanism Register structure with a dual-ended write mechanism

2000-02-18

2001-05-01

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S154000, C365S156000

Reexamination Certificate

active

06226217

ABSTRACT:

RELATED APPLICATIONS
This application is related to co-pending and commonly assigned patent application Ser. No. 09/505,561 entitled “SYSTEM AND METHOD FOR ENABLING/DISABLING SRAM BANKS FOR MEMORY ACCESS,” and co-pending and commonly assigned U.S. Patent application Ser. No. 09/507,333 entitled “MULTI-PORTED REGISTER STRUCTURE UTILIZING A PULSE WRITE MECHANISM,” the disclosures of which are hereby incorporated herein by reference.
TECHNICAL FIELD
This invention is related in general to a register structure, and in specific to a register structure having a dual-ended write mechanism that requires a small amount of circuitry to enable a port coupled to a memory cell of the register structure to perform write operations to such memory cell.
BACKGROUND
Computer systems may employ a multi-level hierarchy of memory, with relatively fast, expensive but limited-capacity memory at the highest level of the hierarchy and proceeding to relatively slower, lower cost but higher-capacity memory at the lowest level of the hierarchy. At the highest level of the memory hierarchy, computers commonly have register structures implemented, which are typically limited in capacity but provide very fast access thereto. Such register structures may be referred to as “register files,” and various such register structures may be implemented for a system, such as an integer register structure and floating point register structure. A register structure enables high speed memory access, and is typically capable of satisfying a memory access request (e.g., a read or write request) in one clock cycle (i.e., one processor clock cycle). Various lower levels of memory may be implemented including a small fast memory called a cache, either physically integrated within a processor or mounted physically close to the processor for speed, as well as the main memory (e.g., the disk drive) of a computer system.
Static random access memory (SRAM) is typically implemented for register structures of a computer system for storing data therein. Generally, SRAM memory is a type of memory that is very reliable and very fast. Unlike dynamic random access memory (DRAM), SRAM does not need to have its electrical charges constantly refreshed. As a result, SRAM memory is typically faster and more reliable than DRAM memory. Unfortunately, SRAM memory is generally much more expensive to produce than DRAM memory. Due to its high cost, SRAM is typically implemented only for the most speed-critical parts of a computer, such as for register structures. However, SRAM memory may be implemented for other memory components of a computer system, as well. Moreover, types of memory other than SRAM (e.g., other types of RAM) may be implemented within a computer system for a register structure.
To enable greater efficiency in processing instructions, multiple ports are commonly implemented within a computer system. For instance, multiple ports may be implemented such that each port is capable of satisfying a memory access request (e.g., a read or write instruction) in parallel with the other ports satisfying such a memory access request. Accordingly, various register structures have been developed to enable access thereto by multiple ports. That is, multi-ported register structures are commonly implemented in the prior art to enable multiple ports to access the register structure to satisfy a memory access request.
Register structures of the prior art are typically implemented with dual-ended writes through an N-channel field effect transistor (NFET) into a latch.
FIG. 1A
illustrates a typical dual-ended SRAM cell
100
of the prior art. The exemplary implementation of
FIG. 1A
illustrates a multi-ported SRAM structure, which comprises a typical SRAM cell comprising cross-coupled inverters
126
and
128
for storing data (i.e., for storing one bit of data). Additionally, NFETs
102
and
112
are provided, which enable writes from a first port (i.e., port
0
). That is, a write is accomplished to the SRAM cell by passing a voltage level across NFETs
102
and
112
into the cross-coupled inverters
126
and
128
. Also, a second port (i.e., port
1
) is coupled to the SRAM cell
100
by implementing NFETs
122
and
124
, which enable writes from the second port to the SRAM cell
100
. The multi-ported SRAM structure
100
of
FIG. 1A
is well-known in the art and is commonly implemented in integrated circuits of the prior art. The SRAM cell
100
of
FIG. 1A
is a memory cell capable of storing one bit of data (i.e., a logic 1 or a logic 0). Thus, many of such SRAM cells
100
are typically implemented within a system to provide the desired amount of SRAM memory.
Either of the two ports (i.e., port
0
and port
1
) coupled to the SRAM cell
100
may write data into the cell to satisfy a memory write request. As shown, BIT_P
0
, NBIT_P
0
, and WORD_
0
lines are implemented to enable a write for port
0
to the SRAM cell
100
, and BIT_P
1
, NBIT_P
1
, and WORD_P lines are implemented to enable a write for port
1
to the SRAM cell
100
. The BIT_P
0
and BIT_P
1
lines may be referred to herein as data carriers for port
0
and port
1
, respectively, and NBIT_P
0
and NBIT_P
1
may be referred to herein as complementary data carriers for port
0
and port
1
, respectively. The operation of this prior art implementation is well known in the prior art, and therefore will be described only briefly herein. Typically, the BIT_P
0
and BIT_P
1
lines are held to a high voltage level (i.e., a logic 1), unless one of them is actively pulled to a low voltage level (i.e., a logic 0). For instance, when writing data from port
0
to the SRAM cell
100
, the BIT_P
0
line is actively driven low by an outside source (e.g., an instruction being executed by the processor) if the outside source desires to write a 0 to the SRAM cell
100
, and the NBIT_P
0
line is held to a high voltage level (the opposite of BIT_P
0
). Otherwise, if an outside source desires to write a 1 to the SRAM cell
100
, the BIT_P
0
line remains high and the NBIT_P
0
line is pulled low. Thereafter, the WORD_
0
line is fired (e.g., caused to go to a high voltage level), at which time the value of the BIT_P
0
line is written into the SRAM cell
100
. More specifically, the voltage level of BIT_P
0
is transferred across NFET
102
and the voltage level of NBIT_P
0
is transferred across NFET
112
to accomplish a write of the value of BIT_P
0
to DATA of the cross-coupled inverters
126
and
128
.
A similar operation is performed when writing data from port
1
to the SRAM cell
100
. For instance when writing data from port
1
to the SRAM cell
100
, the BIT_P
1
line is actively driven low by an outside source (e.g., an instruction being executed by the processor) if the outside source desires to write a 0 to the SRAM cell
100
, and the NBIT_P
1
line is held to a high voltage level (the opposite of BIT P
1
). Otherwise, if an outside source desires to write a 1 to the SRAM cell
100
, the BIT_P
1
line remains high and the NBIT_P
1
line is pulled low. Thereafter, the WORD_
1
line is fired, at which time the value of the BIT_P
1
line is written into the SRAM cell
100
. More specifically, the voltage level of BIT_P
1
is transferred across NFET
122
and the voltage level of NBIT_P
1
is transferred across NFET
124
to accomplish a write of the value of BIT_P
1
to DATA of the cross-coupled inverters
126
and
128
. The data value written into the SRAM cell
100
(e.g., a logic 0 or logic 1) is shown as DATA in
FIG. 1A
, and the complement of such value is shown as NDATA. The SRAM register structure illustrated in
FIG. 1A
is referred to as a dual-ended write structure because it utilizes two lines to write a data value into the SRAM cell
100
. For instance, it requires both a data carrier and a complementary data carrier (e.g., BIT_P
0
and NBIT_P
0
) to write a value to the SRAM cell
100
from port
0
, and it requires both a data carrier and a complementary data carrier (e.g., BIT_P
1
and NBIT_P
1
) to write a value to the SRAM cell
100
from port
1
.
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