Register rotation prediction and precomputation

Details Register rotation prediction and precomputation Register rotation prediction and precomputation

2006-05-23

2006-05-23

Tsai, Henry W. H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C712S219000

Reexamination Certificate

active

07051193

ABSTRACT:
Instruction-level parallelism in software pipelined loops is exploited by predicting future register rotations. A processor includes an architected current frame marker register and at least one unarchitected frame marker register. Register rotation prediction is achieved by setting the register rotation of future iterations of a software loop to be a function of the unarchitected frame marker registers. True data dependencies remain, but the dependencies caused solely by register renaming are removed. Dynamic predication is used to predicate instructions from future iterations, allowing them to be squashed if dependencies are later found. The register renaming that results from the prediction can be included in instructions in a buffer, or a renaming stage in an execution pipeline can perform the renaming.

REFERENCES:
patent: 4342084 (1982-07-01), Sager et al.
patent: 5142634 (1992-08-01), Fite et al.
patent: 5224210 (1993-06-01), Pinedo et al.
patent: 6151671 (2000-11-01), D'Sa et al.
patent: 6339822 (2002-01-01), Miller
patent: 6351805 (2002-02-01), Janik et al.
patent: 6357016 (2002-03-01), Rodgers et al.
Aiken, A., et al., “Optimal Loop Parallelization”,SIGPLAN Notices, vol. 23 (7), ACM Press, 308-317, (Jul. 1988).
Dehnert, J.C., et al., “Overlapped Loop Support in the Cydra 5”,ASPLOS-III Proceedings Third Internation Conference on Architectural Support for Programming Languages and Operating Systemts, 26-38, (Apr. 1989).
Ebcioglu, K., “A Compilation Technique for Softawre Pipelining of Loops with Conditional Jumps (Preliminary Version)”,Proceedings of the 20th Annual Workshop on Microprogramming and Microarcitechture, 69-79, (Dec. 1987).
Rau, B.R., “Iterative Modulo Scheduling”,International Journal of Parallel Programming24 (1), 3-64, (Feb. 1996).
Rau, B.R., et al., “Code Generation Schema for Modulo Scheduled Loops”,SIG MICRO Newsletter23 (1) (2) , 158-159, (Dec. 1992).
Rau, B.R., et al., “Some Scheduling Techniques and an Easily Schedulable Horizontal Architechture for High Performance Scientific Computing”,14th Annual Microprogramming Workshop, 183-198, (Oct. 1981).

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