Register providing simultaneous reading and writing to multiple

Details Register providing simultaneous reading and writing to multiple Register providing simultaneous reading and writing to multiple

1986-03-19

1988-01-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365154, G11C 700

Patent

active

047195967

ABSTRACT:
A memory cell that allows simultaneous writing into the cell and reading from the cell. The memory cell is a cross-coupled latch in which two pairs of a load transistor and a pull-down transistor are connected at respective first and second coupling points. However, the feedback path from the first coupling point to the gate electrode of the pull-down transistor of the other pair passes through a feedback transistor which can thus selectively open this feedback path. In any access to the memory cell, the feedback path is interrupted. Any one of a plurality of write signals can be impressed upon the gate electrode of the thus separated gate electrodes. Simultaneously, the signal on the first coupling point can be selectively impressed upon any combination of a plurality of read lines. If a simultaneous writing and reading is being performed, the write signal passes immediately through the memory cell to the read lines.

REFERENCES:
patent: 3440444 (1969-04-01), Rapp
patent: 4542483 (1985-09-01), Procyk
patent: 4554645 (1985-11-01), Furman
patent: 4577292 (1986-03-01), Bernstein
patent: 4599708 (1986-07-01), Schuster
IBM Technical Disclosure Bulletin, vol. 26, No. 7B, Dec. 1983, pp. 3626-3627, by M. N. Shen.

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