Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2003-01-24
2004-07-20
Auduong, Gene N. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S229000
Reexamination Certificate
active
06765839
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a refresh circuit having a variable restore time according to an operating mode of a semiconductor memory device and a refresh method of the same.
2. Discussion of the Related Art
A semiconductor memory device such as a dynamic random access memory (DRAM) includes memory cell circuits, each of which consists of one transistor and one capacitor. In the DRAM, while a data is stored in the capacitor, the data can be temporarily retained for several milliseconds. Therefore, the memory cells of the DRAM need to be periodically refreshed. In general, the refresh operation is performed between memory access operations so that an execution of operations requested by a central processing unit (CPU) cannot be interrupted. A refresh circuit must drive respective word lines of the DRAM within a refresh time by one time and a counter must drive the word lines by sequentially incrementing an address of the word lines. During a refresh cycle, the CPU cannot utilize the DRAM and a memory controller controls a memory use request of the CPU and a request of the refresh circuit.
Meanwhile, the refresh operation can be achieved when a chip select signal (CSb) is activated or inactivated to an active state or a standby state, respectively. A data restore time for refreshing a memory cell data is equal in both the active state and the standby state. Therefore, in the standby state of the DRAM, if a refresh time is prolonged by extending the data restore time, it is possible to secure a margin for sufficiently refreshing the memory cell data. In addition, there is an advantage that the standby state of the DRAM can be fully utilized.
Accordingly, there is a demand for a refresh circuit having different restore times in the active state and the standby state of the DRAM.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a refresh circuit capable of extending a refresh time in a standby state of a semiconductor memory device is provided.
According to another aspect of the present invention, a refresh method of a semiconductor memory device is provided.
The refresh circuit in accordance with the present invention includes a self-refresh oscillator, a refresh pulse generating unit, a standby refresh signal generating unit and a word-line pulse generating unit. The self-refresh oscillator generates a clock signal having a predetermined period and a refresh pulse generating unit receives the clock signal to generate first and second refresh signals. The standby refresh signal generating unit receives the second refresh signal and a chip select signal to generate a standby refresh signal, in which the chip select signal is a signal representing an active state and a standby state of a semiconductor memory device. The word-line pulse generating unit receives the first refresh signal and the standby refresh signal to generate a word-line driving signal. A pulse width of the word-line driving signal generated at the standby state is longer than that of the word-line driving signal generated at the active state.
The self-refresh oscillator includes an inverter chain unit including an odd number of inverters; a buffer unit for buffering an output of the inverter chain unit to generate the clock signal; and a delay unit coupled between a first inverter and a final inverter among the odd number of the inverters. The inverter chain unit further includes a cutoff unit coupled between an output of a first inverter and a ground voltage and between an output of a final inverter and a power supply voltage, wherein the first and final inverters are contained in the odd number of the inverters. The refresh pulse generating unit includes a first delay chain unit for delaying the clock signal by a first predetermined time; a first NOR gate for receiving the clock signal and an output of the first delay chain unit to generate the first refresh signal; a second delay chain unit for delaying an output of the first NOR gate by a second predetermined time; a second NOR gate for receiving the output of the fist NOR gate and an output of the second delay unit; and an inverter for receiving an output of the second NOR gate to generate the second refresh signal.
The standby refresh signal generating unit includes a NAND gate for receiving the second refresh signal and the standby refresh signal; a first inverter for receiving an output of the NAND gate to generate a transmission signal; a second inverter for receiving an output of the first inverter to generate an inverted transmission signal; a first latch unit responsive to the transmission signal and the inverted transmission signal, for receiving a preliminary standby refresh signal; and a second latch unit for receiving an output of the first latch unit to generate the preliminary standby refresh signal and the standby refresh signal in response to the transmission signal and the inverted transmission signal.
The word-line pulse generating unit includes a first delay unit for delaying the first refresh signal by a first predetermined time; a second delay unit for delaying an output of the first delay unit by a second predetermined time; a transmission unit for selectively transmitting the outputs of the first and second delay units in response to the standby refresh signal and an inverted standby refresh signal; a latch unit for latching an output of the transmission unit; a first inverter for receiving an output of the latch unit; a NOR gate for receiving an output of the first inverter and the first refresh signal; and a second inverter for receiving an output of the NOR gate to generate the word-line driving signal.
According to a further aspect of the present invention, there is provided a method for refreshing a semiconductor memory device, comprising the steps of a) generating a clock signal having a predetermined period by an odd number of inverter chains and a delay means; b) changing an operating mode of the semiconductor memory device from an active state to a standby state in response to a chip select signal; c) generating first and second refresh signals in response to the clock signal, the first and second refresh signals having first and second pulse widths, respectively; d) generating a standby refresh signal in response to the second refresh signal and the chip select signal, the chip select signal indicating that the operating mode is changed to the standby state; and e) generating a word-line driving signal in response to the first refresh signal and the standby refresh signal. At this time, a pulse width of the word-line driving signal generated at the standby state is longer than that of the word-line driving signal generated at the active state.
In accordance with the present invention, since the refresh time is long at the standby state, a sufficient refresh can be achieved at each memory cell and the power consumption needed for the refresh operation can reduced.
REFERENCES:
patent: 6134167 (2000-10-01), Atkinson
patent: 6285578 (2001-09-01), Huang
patent: 6625077 (2003-09-01), Chen
patent: 2004/0027888 (2004-02-01), Kurita
Auduong Gene N.
F. Chau & Associates LLC
Samsung Electronics Co,. Ltd.
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