Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1974-06-19
1977-11-08
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
307238, 365154, 365179, G11C 706, G11C 1140
Patent
active
040577899
ABSTRACT:
An improved random access word addressable monolithic memory having a storage cell for each binary bit of each binary word of storage capacity. The storage cells being arranged in groups. Each cell of any given group being adapted to store a binary bit corresponding to a given bit position of each word stored in said memory. Each cell of each group being connected via first and second bit lines to a sense amplifier. Each sense amplifier coupled to a reference voltage source. The magnitude of the reference voltage supplied by the reference voltage source bearing a substantially invariant mathematical relationship to first and second potentials manifested by said storage cells during a read mode.
The storage cells may each be generally of the type disclosed and claimed in U.S. Pat. No. 3,423,737 entitled "Non Destructive Read Transistor Memory Cell" granted Jan. 21, 1969 to L. R. Harper and of common assignee with the instant application.
REFERENCES:
patent: 3614753 (1971-10-01), Walhstrom
patent: 3745539 (1973-07-01), Davidson et al.
patent: 3909631 (1975-09-01), Kitagawa
Spadavecchia Richard I.
Struk James R.
DeBruin Wesley
Hecker Stuart N.
International Business Machines - Corporation
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