Reference clock generating circuit in memory to be asynchronousl

Details Reference clock generating circuit in memory to be asynchronousl Reference clock generating circuit in memory to be asynchronousl

1997-10-24

1999-08-17

Nelms, David

Static information storage and retrieval

Read/write circuit

Precharge

365233, 3652335, 365191, G11C 700

Patent

active

059403365

ABSTRACT:
A reference clock generating circuit and method, the circuit having an OR unit for ORing signals, from plural address change defectors, indicative of a change in an inputted address to provide an OR-result on a common terminal; a delay unit for delaying the signals on the common terminal for a predetermined time; a pull-up unit for pulling-up an output potential on the common terminal according to an output signal of the delay unit; and a stabilizing unit for stabilizing a signal on the common terminal.

REFERENCES:
patent: 4355377 (1982-10-01), Sud et al.
patent: 5598375 (1997-01-01), Yang et al.
patent: 5604712 (1997-02-01), Priebe
patent: 5654927 (1997-08-01), Lee
Sow T. et al., A 25-ns Low-Power Full CMOS 1-Mbit (128Kx8) SRAM, Sow T. Chu et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1078-1083.

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