Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1990-07-12
1991-06-11
Moffitt, James W.
Static information storage and retrieval
Read/write circuit
Bad bit
365185, 365210, G11C 2900
Patent
active
050238396
ABSTRACT:
An improved semiconductor memory device having a memory array, a dummy cell and a redundancy cell column is disclosed. At least one dummy capacity cell is connected to the reference bit line to which the dummy cell is connected, and also to a redundancy bit line to which redundancy cells are connected. Therefore, since a capacity on the reference bit line is roughly equalized to that on the redundancy bit line by these dummy capacity cells, it is possible to prevent erroneous potential level determination by a sense amplifier for comparing both the potentials on both the bit lines, without being subjected to the influence of supply voltage fluctuations.
REFERENCES:
patent: 4817052 (1989-03-01), Shinoda et al.
patent: 4885720 (1989-12-01), Miller et al.
Miyamoto Junichi
Ohtsuka Nobuaki
Suzuki Noriaki
Kabushiki Kaisha Toshiba
Moffitt James W.
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