Redundant oscillator distribution in a multi-processor...

Details Redundant oscillator distribution in a multi-processor... Redundant oscillator distribution in a multi-processor...

2007-12-11

2007-12-11

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S401000, C713S500000

Reexamination Certificate

active

11056009

ABSTRACT:
The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) (14) and the wiring (17) from there to multiple, PLL-(12) free clock chips (22) is provided. Instead of only one DCSC (14) and one single wiring (17), two of them (14-0, 14-1; 17-0, 17-1) are used combined with a further particular logic present on each clock chip (22), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.

REFERENCES:
patent: 4696019 (1987-09-01), Tulpule et al.
patent: 4823262 (1989-04-01), Calle
patent: 5517638 (1996-05-01), Szczepanek
patent: 5586308 (1996-12-01), Hawkins et al.
patent: 6069512 (2000-05-01), Rodriguez et al.
patent: 6675307 (2004-01-01), Heitkamp et al.

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